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Integrated First Degree

B.E.(Chemical)
B.E.(Civil)
B.E.(Computer Science)
B.E.(Electrical and Electronics)
B.E. (Electronics and Computer )
B.E.(Electronics and Communication)
B.E.(Electronics and Instrumentation)
B.E.(Manufacturing Engineering)
B.E.(Mechanical)
BE Pharmaceutical Engineering
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M.Sc.(Biological Sciences)
M.Sc.(Chemistry)
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M.Sc. Semiconductor and Nanoscience
M.Sc.(Economics)
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M.Sc.(Physics)
B. E. (Mathematics and Computing)

Higher Degree

M.E.(Electrical with specialization in Power Electronics and Drives)
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M.E.(Biotechnology)
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M.E.(Civil with specialization in Transportation Engineering)
M.E.(Computer Science)
M.E.(Design Engineering)
M.E.(Embedded Systems)
M.E.(Manufacturing Systems Engineering)
M.E.(Mechanical)
M.E(VLSI & Microelectronics)
M.E. Environmental engineering
M.E.(Sanitation Science, Technology and Management)
M.E.(Software Systems)
M.Pharm.(Pharmaceutical Chemistry)
M.Pharm.(Pharmaceutics)
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M.Pharm.(Pharmacy)
M.Sc. General Studies – Communication and Media Studies Stream
Master in Public Health
MBA(Master of Business Administration In Business Analytics)

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Suman Bhowmik

Assistant Professor

Analog Circuits, Power Delivery of IC, SOC Design & Integration, VLSI technology
Office Cabin: D-218, BITS Pilani Goa Campus, Goa- 403726, India
sumanb@goa.bits-pilani.ac.in
0832-2580-834
https://www.linkedin.com/in/dr-suman-bhowmik-a07a4a35/

About the Faculty :

Suman Bhowmik joined BITS after more than nine years in the semiconductor industry at Intel, where he began his career as an SoC Design Engineer. During this period, he contributed to the successful tape-in and tape-out of multiple SoCs and served as a Lead Engineer for Analog component Integration. His cross-domain experience includes SoC-Package co-design, Power and Signal integrity, PDN (Power Delivery Network), System-level simulation, On- Chip Voltage Regulation, Clocking methodology, RTL design, Analog simulation and modelling for SoC integration. He has worked on the latest technology nodes like 14nm, 10nm, 18A etc. His PhD thesis is focused on reducing Power-Supply Noise in Integrated circuits through PDN analysis and low-jitter PLL design. 

Google Scholar: https://scholar.google.com/citations?user=6IVgKSAAAAAJ&hl=en

 

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