ISVLSI’26 "RAGE: A Data-Aware Aggressive Prefetcher for High-Performance Graph Analytics", Varun Venkitaraman, Mitul Tandon, Tejeshwar Bhagatsing Thorawade, Nayan Barhate, Keerthi Sagar Kokkiligadda, Newton, Raj Kumar Choudhary, Virendra Singh, IEEE Computer Society Annual Symposium on VLSI ISVLSI 2026, Kolkata, India, 2026.

VDAT’25 "Spin-TLB: STT-RAM-based Translation Hierarchy for Server Applications in CPUs", T. B. Thorawade, K. Kokkiligadda, V. Venkitaraman, Ankith, Newton, and V. Singh, The 29th International Symposium on VLSI Design and Test, Chandigarh, India, 2025.

DATE’22 "Data-Aware Cache Management for Graph Analytics", Neelam Sharma*, Varun Venkitaraman*, Newton*, Vikash Kumar, Chandan Jha, Design Automation and Test in Europe Conference, 2022, *Equal Contribution, Core-Ranking ’B’.

CAL’21 "Effective Migration Techniques for STTRAM-based Hybrid Caches", Arindam Sarkar*, Newton*, Varun Venkitaraman, and Virendra Singh, IEEE Computer Architecture Letters, *Equal Contribution, Impact Factor: 1.4.

CAL’20 "PIM-GraphSCC: PIM-based Graph Processing using Graph’s Community Structure", Newton, Virendra Singh, and Trevor E. Carlson, IEEE Computer Architecture Letters 2020, Impact Factor: 1.4.

ICCD’19 "Freeflow Core: Enhancing Performance of In-Order Cores with Energy Efficiency", Raj Kumar Choudhary, Newton, Harideep Nair, Rishabh Rawat, and Virendra Singh, The 37th IEEE International Conference on Computer Design, AbuDhabi, United Arab Emirates, November 2019, Core-Ranking ’B’.

GLSVLSI’18 "AB-Aware: Application Behavior Aware Management of Shared Last Level Caches", Suhit Pai, Newton, and Virendra Singh, ACM Great Lakes Symposium on VLSI (GLSVLSI) 2018, Chicago, Illinois, USA, May 2018.

ICCD’17 "DAAIP: Deadblock Aware Adaptive Insertion Policy for High Performance Caching", Newton, Sujit Kumar Mahto, Suhit Pai, and Virendra Singh, The 35th IEEE International Conference on Computer Design, Boston, USA, November 2017, Core-Ranking ’B’.

VDAT’17 "ACAM: Application Aware Adaptive Cache Management for Shared LLC", Sujit Kumar Mahto and Newton, The 21st International Symposium on VLSI Design and Test, Roorkee, India, July 2017.

GLSVLSI’17 "EEAL: Processors’ Performance Enhancement Through Early Execution of Aliased Loads", Abhishek Rajgadia, Newton and Virendra Singh, ACM Great Lakes Symposium on VLSI (GLSVLSI) 2017, Banff, Canada, May 2017.