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Integrated First Degree

B.E.(Chemical)
B.E.(Civil)
B.E.(Computer Science)
B.E.(Electrical and Electronics)
B.E. (Electronics and Computer )
B.E.(Electronics and Communication)
B.E.(Electronics and Instrumentation)
B.E.(Manufacturing Engineering)
B.E.(Mechanical)
BE Pharmaceutical Engineering
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B. E. (Mathematics and Computing)

Higher Degree

M.E.(Electrical with specialization in Power Electronics and Drives)
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M.E.(Computer Science)
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M.E.(Embedded Systems)
M.E.(Manufacturing Systems Engineering)
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M.E. Environmental engineering
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Sanjay K. Sahay

Professor

Applied AI, Applied Cryptography, Blockchain Technology, Information Security, Malware Analysis
Department of Computer Science and Information Systems
ssahay@goa.bits-pilani.ac.in
0832-2580243
https://in.linkedin.com/in/sanjay-k-sahay-15357150

.

Patents Published:

  1. Hardware data-flow integrity monitor with register-file provenance tagging for RISC-V IoT processors.
    Inventors: Jyotiprakash Mishra, Sanjay K. Sahay, Swati Mishra and Aman Pathak
    Application No: 202631036811
    Publication No: IN202631036811 A1
  2. Hardware-accelerated microarchitectural event classifier with programmable feature extraction pipeline and on-chip ensemble inference engine for real-time malware detection in RISC-V processors.
    Inventors: Jyotiprakash Mishra, Sanjay K. Sahay, Swati Mishra and Aman Pathak
    Application No: 202631036812
    Publication No: IN202631036812 A1
  3. Per-peripheral cryptographic session engine with hardware key rotation for RISC-V IoT system-on-chip.
    Inventors: Jyotiprakash Mishra, Sanjay K. Sahay, Swati Mishra and Aman Pathak
    Application No: 202631036813
    Publication No: IN202631036813 A1
  4. On-chip binary decision tree inference engine integrated with RISC-V trace encoder for real-time IoT security monitoring.
    Inventors: Jyotiprakash Mishra, Sanjay K. Sahay, Swati Mishra and Aman Pathak
    Application No: 202631036814
    Publication No: IN202631036814 A1
  5. RISC-V processor architecture with tiered-memory ISA extension, tier-aware translation lookaside buffer, and thunderbolt-attached external dram expansion with RISC-V bridge controller for linux-based heterogeneous memory systems.
    Inventors: Jyotiprakash Mishra, Sanjay K. Sahay, Swati Mishra and Aman Pathak
    Application No: 202631036815
    Publication No: IN202631036815 A1
  6. Programmable instruction fusion engine with SRAM-based rules table for RISC-V IoT processors.
    Inventors: Jyotiprakash Mishra, Sanjay K. Sahay, Swati Mishra and Aman Pathak
    Application No: 202631036816
    Publication No: IN202631036816 A1

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