Prof. S Gurunarayanan

Senior Professor
Department of Electrical and Electronics Engineering

embedded systems, VLSI Architecture, Digital VLSI Design
Birla Institute of Technology & Science, Pilani
Hyderabad Campus
Jawahar Nagar, Kapra Mandal
Dist.-Medchal-500 078
Telangana, India


  • Joined BITS - Pilani in 1987.
  • M.E. & Ph.D. from BITS - Pilani.
  • Involved in Teaching, Research & Administration.
  • Presently Teaching: Digital Design, VLSI Design, VLSI Architecture & Computer Architecture.
  • Research Interest: Digital Design, Embedded Systems & Computer Architecture.


      Ph.D                                                    2000       BITS - Pilani
      M.E                                                     1990         BITS - Pilani
     M.Sc  Physics                                    1987          Alagappa University,  Tamilnadu

Professional Experience

  • From June 2021         Senior Professor
  • 2005  - 2021                Professor
  • 2000 - 2005                Associate Professor
  • 1995 -  2000                Assistant Professor
  • 1991 -   1995                 Lecturer
  • 1990 -  1991                 Assistant Lecturer
  • 1987 -  1990                 Teaching Assistant


Administrative Experience

  • June 2020  Onwards                              Dean, Work Integrated Learning Programmes
  • May 2018        -  June 2020                   Dean, Practice School Division
  • August 2015   - August  2018                Dean, Admissions
  • August 2015   - August 2018                 Dean, Instruction Division
  • May 2011         - May 2018                     Dean, Work Integrated Learning Programmes
  • January 2007 - April 2011                    Dean, Admissions & Faculty Division II 
  • July 2002        - December 2006         Assistant Dean, Engineering Services Division
  • March 1997     - June 2002                   Group Leader, Instrumentation Group
  • January 1994  - June 2002                  Warden, Malviya Bhavan 


Current Semester Courses
On Campus Course
  •  Digital Design
  •  VLSI Architecture
Off Campus Course
  • VLSI Architecture

Courses Taught in Recent Past

On Campus Courses: 
  • Electronics
  • VLSI Design
  • Digital Design
  • VLSI Architecture
  • Analog Electronics
  • Computer Architecture
  • Embedded System Design
  • Advanced VLSI Architecture
  • Advanced Electronic Circuits
  • Microprocessor Based System Design
  • Electron Devices and Integrated Circuits
  • Microprocessor Programming & Interfacing
  • Digital Electronics & Computer Organisation
  • Physics & Modelling of Micro Electronic Devices
Off Campus Courses:
  • VLSI Design 
  • VLSI Architecture

Visits Abroad

  •  Microsoft Research Faculty Summit 2005 
               July 17 -20, 2005  
              Redmond, Washington, USA 
  • The 26th ICDE World Conference: International Council for Open and Distance Education
               October 14- 16,2015
               Sun City, South Africa

Doctoral Students Completed

A   As  Supervisor :

  • Dr. Sai Sesha Chalapathi  
  • Thesis Title:   Time Synchronization and Task - Assignment Algorithms for Specific Domains of the  Internet of Things 
  • Dr. Kiran D.C  
  • Thesis Title:Compiler Optimization Techniques for Multi-Core Embedded Processors  
  • Dr. Nitin Chaturvedi    
  • Thesis Title:   Techniques to improve the performance of Cache Memory for Multi - Core Processors.  
  • Dr. Biju K. Raveendran   
  • Thesis Title Energy Efficient Techniques for Multi-tasking Embedded Systems- Cache Design and Task Scheduling Algorithms"

As  As  Co Supervisor:

      Dr. Jai Gopal Pandey  

  •      Thesis Title:  Architectures and Algorithms for Image and Video Processing        ............................Using  FPGA Platform


Research Project Completed

                Intelligent Water Resource Management

              (Microsoft Research University Relations - India,
              under ICT for Underserved Communities)




  1.  Kanika Monga, Kunal Harbhajanka, Arush Srivastava, Nitin Chaturvedi, S. Gurunarayanan, Design of an MTJ/CMOS based Asynchronous System for Ultra-Low Power Energy Autonomous Applications, Journal of Circuits, Systems and Computers, June,2020. doi: 10.1142/S0218126621500584 



  1.    G.S.S. Chalapathi, Vinay Chamola, Chen-Khong Tham, S. Gurunarayanan and Nirwan Ansari “An                         Optimal Delay   Aware  Task Assignment Scheme for Wireless SDN Networked Edge Cloudlets”    Future                 Generation Computing  Systems.  vol.   102, pp. 862-875, Jan 2020


  1. G.S.S Chalapathi, Vinay Chamola, S Gurunarayanan and Biplab Sikdar, “E-SATS: An Efficient and Simple Time Synchronization Protocol for Cluster-based Wireless Sensor Networks,” IEEE Sensors Journal, vol. 19, no. 21, pp. 10144-10156, 1 Nov.1,2019.


  1. G.S.S Chalapathi, Vinay Chamola and S Gurunarayanan, “A Testbed validated simple time synchronization protocol for clustered wireless sensor networks for IoT,” Journal of Intelligent and Fuzzy Systems, IOS Press, vol. 36, no. 5, pp. 4531-4543,2019


  1.   G.S.S Chalapathi, Bernhard Etzlinger, S Gurunarayanan and Andreas Springer, “Integrated Cooperative Synchronization for Wireless Sensor Networks,” IEEE Wireless Communication Letters, vol. 8, no. 3, pp. 701-704, June2019.


  1. D.C. Kiran, S. Gurunarayanan, Janardan Prasad Misra, and Abhijeet Nawal ," Global Scheduling Heuristics for Multicore Architecture", Hindawi Publishing Corporation, Scientific Programming, Volume2015, Article ID 860891 ,


  1. D.C. Kiran, S. Gurunarayanan, J.P.Misra & Munish Bhathia "Register Allocation for Fine Grained Threads on Multicore Processors".Journal of King Saud University - Computer and Information Sciences, Elsevier,Volume 27, Issue 3 2015.


  1. Nitin Chaturvedi, Arun Subramanian, S Gururnarayanan, “Selective cache line replication scheme in Shared Last Level Cache”, in Procedia of Computer Science, Elsevier, Volume 46, pp.1095-1107, 2015. (Scopus)
  2.   Nitin Chaturvedi, Arun Subramanian, S Gururnarayanan, “   An  Efficient  data  access  policy  for shared last Level      Cache”,   in WSEAS transaction on computers, Volume 14,2015.
  3.     Nitin Chaturvedi, S Gurunaryanan, “An Efficient adaptive block pinning for multi-core architectures”,  in Journal of     Microprocessor and Microsystems, Elsevier, Volume 39, Issue 3,2015(SCI)
  4. Nitin Chaturvedi, S Gurunaryanan “An Adaptive Migration-Replication Scheme (AMR) for      SharedCache in Chip     Multiprocessors” in Journal of Parallel Computing, Springer, Volume 71, Issue   10 pp. 3904-3933,  Oct. 2015. (SCI)
  5. Nitin Chaturvedi, S Gurunaryanan “An A Locality-Aware Variable Granularity Cache Architecture” Electronics Letter-    IET, January 2015
  6.  Nitin Chaturvedi, S Gururnarayanan, “ Adaptive Block Pinning :  A  Novel  Shared  Cache  Partitioning  Techniques for  CMP” in European Journal of Scientific Research, Volume 117, Issue 1, June2014.
  7.  Nitin Chaturvedi, S Gururnarayanan, “ Study of  Various Factors Affecting Performance of Multi-Core Architectures”   in International Journal of Distributed and Parallel Systems, Volume 4, No 4, July2013.


  1. Jai Gopal Pandey, Abhijit Karmakar, Chandra Shekhar and S. Gurunarayanan “Platform - Based   Design Approach    for Embedded Vision Applications”Journal of Image and Graphics Volume 1, No.1,   March 2013. 


  1.    Nitin Chaturvedi, Jithin Thomas, S Gururnarayanan, “ Adaptive Block Pinning Based :  Dynamic Cache Partitioning     for Multi - Core  Architectures”   in  International  Journal of  Computer Science  &  Information  Technology       (IJCSIT),     Volume  2,    No 6, December2010.
  2.  Nitin Chaturvedi, Jithin Thomas, S Gururnarayanan, “Adaptive Zone-Aware Multi-bank on Chip last level L2 cache     Partitioning for Chip Multiprocessors” in International Journal of Computer Applications ,Volume 6, No-9,           September 2010.
  3. Biju Raveendran, T S B Sudarshan, and S Gurunarayanan. “Cache Memory Design with Late Replacements for       Embedded Systems”International Journal of Lateral Computing, Vol.2, No. 2, August 2006.


  1.  A K Singh, S Gurunarayanan, V Ramachandran and M Umashankar. “Edge Potential Effects on the operation  of short   channel devices”Microelectronics International Vol.20, Number 3, 2003.


  1.  Pranshu, Shaishta, Nitin, S Gurunarayanan, “An Exploration of Neuromorphic Systems and Related Design Issues/Challenges in Dark Silicon Era” in 3rd International Conference on Communication Systems, ICCS-2017,14-16 October 2017, PilaniIndia.


  1. Suvi Jain, Nitin Chaturvedi, S Gurunarayanan, “Design and Analysis of 6T SRAM Cell with NBL Write Assist Technique Using FinFET” in International Conference on Computer, Communications and Electronics, COMPTELIX 2017,1-2 July 2017,Jaipur,India .(IEEE-Xplore)


  1. Divya Suneja, Nitin Chaturvedi, S Gurunarayanan, “A Comparative Analysis of Read/Write Assist   Techniques on Performance & Margin in 6T SRAM Cell Design” in International Conference on   Computer, Communications and Electronics, COMPTELIX 2017, 1-2, July 2017,  Jaipur,             India(IEEE -Xplore)


  1. Nikunj, Nitin Chaturvedi, S Gurunarayanan, “Design Of Non-Volatile Asynchronous Circuit Using CMOS-FDSOI/FinFET Technologies” in IEEE International Conference on Computing, Analytics and Security Trends, CAST-2016, 19-21 December 2016, Pune, India (IEEE-Xplore)


  1.  Pranshu, Shaishta, Nitin Chaturvedi, S Gurunarayanan, “An Investigation of Power- Performance Aware     Accelerator/Core Allocation Challenges in Dark Silicon Heterogeneous Systems” in 2nd IEEE International       symposium on nanoelectronic and information systems, IEEE-INIS-2016, 19-21 December 2016,IIITM    Gwalior,India (IEEE-Xplore) 


  1.       GSS Chalapathi,  R. Manekar,  V. Chamola,  K.R. Anupama  and  S Gurunarayanan, "Hardware   

                Validated   Efficient  Simple Time Synchronization Protocol for clustered WSN," IEEE TENCON,                            2016, Singapore, Nov. 22- 25, 2016.


  1.  R. Manekar, GSS Chalapathi, V. Chamola, K.R. Anupama and S Gurunarayanan,

              “A Simple Time Synchronization Algorithm for WSNs in Smart Grid Applications,”

               IEEE Symposium on Emerging  Topics in Smart and Sustainable  Grids, Singapore, Sept. 2016  


  1.   J. G. Pandey,  A. Karmakar,  C. Shekhar,  and S. Gurunarayanan,  An Embedded   Frame work  

            for Accurate Object Localization using Center of Gravity Measure with Mean Shift                                                       Procedure, IEEE 19th International Symposium on   VLSI  Design and Test,  

           Ahmedabad,   India, 26-29 June 2015,   pp. 1-6.


  2.  J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan,    “Architectures  for      Embedded   Vision Application using FPGA-based Platform” IEEE 28th Int’l Conf. on VLSI Design and  14th Int’l Conf. on Embedded Systems (VLSI Design 2015), BangaloreIndia, 3-7 Jan. 2015. 



  1.  J.G. Pandey, A Karmakar, C Shekhar, S Gurunarayanan, “An FPGA-based architecture for local  similarity measure for image/video processing applications” 2015, 28th International Conference  on  VLSI Design, 339-344, BangaloreIndia. 



  1.    J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, Architectures and algorithms for    image and video processing using FPGA-based platform IEEE 18th International Symposium on  VLSI Design and Test, CoimbatoreIndia,16-18 July 2014  pp.1-1 


  1. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “A novel architecture for FPGA   implementation of Otsu’s global automatic image thresholding algorithm,” in Proceedings of IEEE 27th International Conf. on VLSI Design and 13th International Conf. on Embedded Systems        (VLSI Design 2014), MumbaiIndia, 5-9 Jan. 2014, pp. 300-305. (IEEE Xplore) [Impact  factor: 0.40]   (For  Year 2012)



  1. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “An FPGA-based architecture for   kernel-smoothed local histogram computation,”Accepted for publication in IEEE International    Symposium on Circuits and Systems (ISCAS-2014)Melbourne, Australia, 01-05 June, 2014.         (IEEE   -  Xplore) [Impact factor: 0.27] (For Year 2012). 



  1.    J. G. Pandey, A. Karmakar, A. K. Mishra, C. Shekhar, and S. Gurunarayanan, “Implemention    of an  improved connected component labeling algorithm using FPGA based platform,” Accepted for  Publication in IEEE International Conf. on Signal Processing and  Communications (SPCOM, 2014), IISc-Bangalore, India, 22-25 July 2014. (IEEE- Xplore)



  1.  J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “An FPGA-based novel           architecture for the fixed-point binary antilogarithmic computation,” in Proceedings of IEEE  International Conf. on Electronic Systems, Signal Processing and Computing Technologies        (ICESC),  Nagpur, India,     09-11 Jan. 2014, pp. 23-28. (IEEE- Xplore[Best Paper Award]



.              16.    J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “An FPGA-based

            fixed-point  architecture for binary logarithmic computation,” in 

            Proceedings of 2nd IEEE International   Conf.  in Image Information Processing (ICIIP-2013)

            ShimlaIndia, 09-12 Dec. 2013, pp.    383- 388. (IEEE -Xplore)



  1. Nitin Chaturvedi, S Gurunarayanan, “An Adaptive Block Pinning Cache for Reducing Network   Traffic in Multi-Core Architectures” 2013 IEEE International Conference on Computational Intelligence and Communication Network, ICCN- 2013, September 27-29, 2013Mathura, India (IEEE –Xplore)



  1.  Nitin Chaturvedi, S Gurunarayanan, “An Adaptive Cache Coherence Protocol with adaptive Cache for Multi-core Architectures” in proceedings of International Conference on Advanced Electronic Systems, ICAES-2013 September 21-23, 2013, CEERI, Pilani,India (IEEE –Xplore) 



  1.   Munish Bhathia, D.C.Kiran, S Gurunarayanan, and J.P.Misra, "Fine Grain Thread Scheduling on     Multicore Processors: Cores With Multiple Functional Units". Compute '13: Proceedings of the      6th  ACM India Computing Convention, Vellore, Tamilnadu, India. August 2013 Article No.:        20  Pages  1–6 .              doid=2522548.2523137



  1. D.C. Kiran, S. Gurunarayanan, J.P.Misra, and D.Yashas "Integrated Scheduling and Register        Allocation For Multicore Architecture". In IEEE Conference on Parallel Computing Technologies  PARCOMPTECH-2013, Organized by C-DAC in IISC Bangalore, February  2013.



  1. D.C. Kiran, S. Gurunarayanan, and J.P.Misra, Compiler Driven Inter Block Parallelism for Multicore Processors. In 6th International Conference on Information Processing, published in the Communications in Computer and Information Science (CCIS), Springer-Verlag, Bangalore, India, August 2012.  




  1.  D.C. Kiran, S. Gurunarayanan, Faizan Khaliq, and Abhijeet Nawal, Compiler Efficient and Power Aware Instruction Level Parallelism for Multicore Architectures. In The International Conference of Eco-friendly Computing and Communication Systems, (ICECCS) 2012, Kochi, India, August 9-11, 2012. Proceedings published in the Communications in Computer and Information Science (CCIS), Springer-Verlag, pp.9-17



  1. D.C. Kiran, S. Gurunarayanan, J.P.Misra and Faizan Khaliq, An Efficient Method to Compute Static Single Assignment Form for Multicore Architecture.In 1st IEEE International Conference on Recent Advances in Information Technology, Dhanbad, India. March, 2012. pp. 776-789,



  1. Nitin Chaturvedi, Prashant Gupta, S Gurunarayanan, “Efficient Cache Migration Policy for Chip Multi-Processors” 2011 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC-11, 15-18 December 2011.Kanyakumari, Tamilnadu, India.



  1. D.C. Kiran, S. Gurunarayanan, and J.P.Misra,Taming Compiler to Work with Multicore Processors. IEEE Conference on Process Automation, Control and Computing.  Coimbatore,  Tamilnadu, India  20-22  July  2011. 



  1. D.C.Kiran, B. Radheshyam. Gurunarayanan, and J.P.Misra, Compiler Assisted Dynamic   Scheduling for Multicore Processors. IEEE Conference on Process Automation, Control and  Computing, Coimbatore, Tamilnadu, India, July,20- 22,   2011.



  1. Nitin Chaturvedi, Pradeep Harinderan, S Gururnarayanan, “A Novel shared L2 NUCA cache       partitioning scheme for Multi-core Architectures” in proceedings of International Conference on   Emerging Trends in Engineering (ICETE),Maharashtra, India, Feb.20-21, 2010.pp. 183-188.



  1.            Biju Raveendran , Sundar Balasubramaniam , and S. Gurunarayanan. “Evaluation of Priority   Based Real Time Scheduling Algorithms: Choices and Tradeoffs.” In Proceedings of the 23rd  Annual ACM Symposium on Applied Computing (ACM SAC'08), Brazil, Mar-2008, vol. 1, pp.    302 - 307. 



  1.  Biju Raveendran, T S B Sudarshan, Avinash Patil, Komal Randive, and

            S Gurunarayanan. “Predictive    Placement Scheme for Set-Associative Cache for Energy  Efficient   Embedded System.” Proceedings of International Conference on Signal Processing, Communications  and Networking, (ICSCN 2008),January 4-6, 2008, Chennai,

               Tamilnadu, India pp. 152-157,   Available online in IEEEXPLORE.



  1. Biju Raveendran, T S B Sudarshan, Dlip Kumar, Priyanaka Tugudu and S Gurunarayanan. “LLRU: Late LRU Replacement Strategy for Power Efficient Embedded Cache.”Proceedings of 15th IEEE              International Conference On Advanced Computing (ADCOM), IIT-Kharagpur,India Dec-2007,  pp. 339-344, Available online in IEEEXPLORE.



  1.  Biju Raveendran, T S B Sudarshan, Avinash Patil, Komal Randive, and S Gurunarayanan. “An     Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded   System.” Proceedings of ESA'07- The 2007 International Conference on Embedded Systems   and  Applications, USA, (Published by CSREA Press, Jun-2007, pp. 188–194.



  1. Biju Raveendran, J P Misra, Karan Bhatnagar and S Gurunarayanan. “EFFS: Efficient Flash File   System for Wireless Sensor Nodes.” Proceedings of ESA'07- The 2007 International

         Conference  on Embedded Systems and Applications, USA, (Published by CSREA Press,

          Jun-2007, pp. 159– 165. 




  1. Biju Raveendran, T S B Sudarshan, and S Gurunarayanan. “Selective Placement Data Cache for   Low  Energy Embedded System”. Proceedings of 14th IEEE International Conference On      Advanced   Computing (ADCOM), NITK, Surathkal, India. Dec-20-23, 2006, pp. 473-476,  Available online  in IEE-EXPLORE. 




  1.  Ninad B Kothari, T S B Sudarshan, S Gurunarayanan, and S Chandrashekhar. “SoC Design of a   Low  Power Wireless Sensor Network Node for Zigbee Systems.” Proceedings of 14th IEEE   International Conference On Advanced Computing (ADCOM),  NITK, Surathkal, India.  Dec- 20-23-2006, pp.  462-466. Available online in IEE-EXPLORE.



  1.  Biju Raveendran , Sundar Balasubramaniam , K Durga Prasad and S. Gurunarayanan. “Variants of  Priority Scheduling Algorithms for Reduced Context Switches in Real Time System.”8th   International Conference on Distributed Computing and Networking (ICDCN), Lecture  Notes in Computer Science, Springer-Verlag. IIT - GuwahatiIndia.Dec-2006, pp. 466-478.



  1.  Biju Raveendran , Sundar Balasubramaniam , K Durga Prasad and S. Gurunarayanan. “A Context-  Switch Reduction Heuristic for Power-Aware Off-line Scheduling.” 11th Asia-Pacific Computer  Systems Architecture Conference (ACSAC), Lecture Notes in Computer Science, Vol. 4186,    Springer-Verlag. ShanghaiChina, Sep-2006, pp. 404-411.



  1.  Ninad B Kothari, T S B Sudarshan, Shipra Bhal, Tejesh E C, and S Gurunarayanan. “Design of an  Efficient Low-Power AES Engine for Zigbee Systems.” Proceedings of 10th IEEE VLSI Design &   Test Symposium (VDAT), Goa, India. Aug-2006, pp. 264-272. 




  1. Biju Raveendran, T S B Sudarshan, and S Gurunarayanan. “Cache Memory Design with Late  Replacements for Embedded Systems.” Proceedings of 2nd International Conference on        Embedded  Systems, Mobile Communication and Computing (ICEMC2), Bangalore, India.  Aug-  2006, pp. 76- 90.



  1. Gurunarayanan , R Mehrotra and S Chandrashekhar. “Modelling of ESD Protection                                                          Circuits.”Proceedings of 8th International Workshop on Physics of Semiconductor

               Devices,  New Delhi, India. 1995.



  1.   Gurunarayanan , R Mehrotra and S Chandrashekhar.”Drain Induced Barrier lowering in short channel NMOS Devices.”Proceedings of 7th International Workshop on Physics of Semiconductor  Devices. New Delhi, India Dec. 14-18, 1993. 75-76.  Narosa Publishing House, 1994