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Vipin Joshi

Assistant Professor, Gr-I

Gallium Nitride High Electron Mobility Transistors, Modeling and simullation of next generation power semiconductor devices, Power Semiconductor Devices, TCAD based reliability physics analysis, Wide bandgap semiconductors
Office: D-112, EEE Department, BITS-Pilani, K. K. Birla Goa Campus, NH 17B, Bypass Road, Zuarinagar, Goa - 403726

Patents

Mayank Shrivastava and Vipin Joshi, “Doping and Trap Profile Engineering in GaN Buffer To Maximize AlGaN/GaN HEMT Epi Stack Breakdown Voltage”, US Patent No (08-06-2021):11,031,493 (Indian Patent Application 201841020899, Filed on June 5th, 2019)