Dr. Chetan Kumar Vudadha

Assistant Professor
Department of Electrical and Electronics Engineering

CNFET based MVL Circuits, Computer Arithmetic, FPGA based System Design
H231, Department of Electrical and Electronics Engineering, BITS-Pilani
Hyderabad Campus
Jawahar Nagar, Kapra Mandal
Dist.-Medchal-500 078
Telangana, India

Sponsored Projects

Completed Projects

Start-up Research Grant (SRG) Sponsored by DST-SERB

Role: Principal Investigator
Cost: Rs. 9 Lakhs 
Title: A Novel 2:1 Multiplexer based Approch to Implement Ternary Logic Circuits
Duration: 2 Years, Jan 2021 - Jan 2023
Outcomes: (Novel Designs of 2:1 Multiplexer based Combinational and Sequential Circuits)
  • "Novel Design Methodologies for CNFET-Based Ternary Sequential Logic Circuits", published in IEEE Transactions on Nanotechnology, vol. 21, pp. 289-298, 2022.
  • "Low-Power Approximate Ternary Multiplier using CNFETs" (To be Submitted.)
  • "Design of CNTFET-Based Ternary Logic Circuits Using Low Power Encoder"( Selected for iSES 2022).
  • "Design of Ternary Conditional-Sum Adders" (Manuscript Under Preparation).
Additional Competitive Research Grant Sponsored by BITS-Pilani

Role: Principal Investigator
Cost: Rs. 4.7 Lakhs 
Title: RISC-V based Approximate Processor and its FPGA Prototype for Image processing Applications
Duration: 2 Years 9 months, Sept 2019 - June 2022
Outcomes: (RISC V based Approximate Co-processor, ASIC/FPGA Based Designs for Arithmetic Circuits)
  • "Accuracy Reconfigurable Carry Bypass Approximate Adder Integrated as a Co-processor for RISC-V", (Unpublished)
  • "An Approximate Adder with Inaccurate Addition of Lower Significant bits" (Unpublished)
  • "Design of Resource Efficient Binary and Floating Point Comparator Using FPGA Primitive Instantiation", (Under Review; Journal of Circuits, Systems and Computers).
  • "FPGA Based Implementation of Approximate Booth Multiplier" (Manuscript Under Preparation)
Research Initiation Grant (RIG) Sponsored by BITS-Pilani

Role: Principal Investigator
Cost: Rs. 2 Lakhs 
Title: Design and Synthesis methodologies for CNFET-based Multi-Valued Logic Circuits
Duration: 2 Years, Jan 2019 - Jan 2021  
Outcomes: (New CNFET based ternary Logic circuits)
  • "A Novel Low Power Ternary Multiplier Design using CNFETs,"  published in 33rd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2020.
  • "Design of CNTFET-Based Ternary ALU Using 2:1 Multiplexer Based Approach,"  published in IEEE Transactions on Nanotechnology, vol. 19, pp. 661-671, 2020.
  • "Design of CNFET-based Low-Power Ternary Sequential Logic circuits," published in 21st International Conference on Nanotechnology (NANO), 2021