Conferences Papers:

1. Pawan Sharma, K.R.Anupama, S Gurunarayanan, “Hardware Accelerators for Classification of Thoracic Disorders: A Survey”, 9th International Congress on Information and Communication Technology; Date: February 19 - 22 2024; Conference Venue: London, United Kingdom
2. Pawan Sharma, K.R.Anupama. S Gurunarayanan, “A Review of Deep Learning Techniques of Chest X-Ray Analysis for Thoracic Disorders”, 8th International Congress on Information and Communication Technology; Date: February 20 - 23 2023; Conference Venue: London, United Kingdom.
3. Kanika Monga, S Aggarwal, N.Chaturvedi and S Gurunarayanan, “A Novel Decoder Design for Logic Computation in SRAM: CiM-SRAM” IEEE 18th India Council International conference, 2021.p1-4.2021
4. K Monga, N,Chaturvedi, S Gurunarayanan,” Design of Low Power Approximate adder based on MTJs for Image Processing Applications” (VLSI-TSA) 2021.
5. K. Monga, N. Chaturvedi and S. Gurunarayanan, "Design of a Low Power 11T-1MTJ Non-Volatile SRAM Cell with Half-Select Free Operation," 2020 IEEE 17th India Council International Conference (INDICON), 2020.
6. K. Monga, N. Chaturvedi and S. Gurunarayanan, "Design of a Robust Logic Gate using Magnetic Tunnel Junction," 2019 IEEE 16th India Council International Conference (INDICON), 2019
7. Mudit Chandaliya, Nitin Chaturvedi and S Gurunarayanan, “An exploration of neuromorphic systems and related design issues/challenges in dark silicon era” 331, 3rd International Conference on Communication Systems (ICCS-2017) 14–16 October 2017.
8. D. Suneja, N. Chaturvedi and S. Gurunarayanan, "A comparative analysis of read/write assist techniques on performance & margin in 6T SRAM cell design," 2017 International Conference on Computer, Communications and Electronics (Comptelix), 2017
9. Suvi Jain, Nitin Chaturvedi, S Gurunarayanan, “Design and Analysis of 6T SRAM Cell with NBL Write Assist Technique Using FinFET” in International Conference on Computer, Communications and Electronics, COMPTELIX 2017,1-2 July 2017 (IEEE-Xplore)
10. GSS Chalapathi, R. Manekar, V. Chamola, K.R. Anupama and S Gurunarayanan, "Hardware Validated Efficient and Simple Time Synchronization Protocol for clustered WSN," IEEE TENCON 2016, Singapore, Nov. 22-25, 2016.
11. R. Manekar, GSS Chalapathi, V. Chamola, K.R. Anupama and S Gurunarayanan, “A Simple Time Synchronization Algorithm for WSNs in Smart Grid Applications,” IEEE Symposium on Emerging Topics in Smart and Sustainable Grids, Singapore, Sept. 2016
12. N. Bhimsaria, N. Chaturvedi and S. Gurunarayanan, "Design of non-volatile asynchronous circuit using CMOS-FDSOI/FinFET technologies," 2016 International Conference on Computing, Analytics and Security Trends (CAST), 2016.
13. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “An Embedded Frame work for Accurate Object Localization using Centre of Gravity Measure with Mean Shift Procedure”, IEEE 19th International Symposium on   VLSI Design and Test, Ahmedabad, India, 26-29 June 2015, pp. 1-6.
14. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “Architectures for Embedded Vision Application using FPGA-based Platform” IEEE 28th Int’l Conf. on VLSI Design and 14th Int’l Conf. on Embedded Systems (VLSI Design 2015), Bangalore, India, 3-7 Jan. 2015.
15. J.G. Pandey, A Karmakar, C Shekhar, S Gurunarayanan, “An FPGA-based architecture for local similarity measure for image/video processing applications” 2015, 28th International Conference on VLSI Design, 339-344, Bangalore, India.
16. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “An FPGA-based architecture for kernel-smoothed local histogram computation,” IEEE International Symposium on Circuits and Systems (ISCAS-2014), Melbourne, Australia, 01-05 June, 2014. (IEEE-Xplore) [Impact factor: 0.27]
17. J. G. Pandey, A. Karmakar, A. K. Mishra, C. Shekhar, and S. Gurunarayanan, “Implemention of an improved connected component labeling algorithm using FPGA based platform,” IEEE International Conf. on Signal Processing and Communications (SPCOM, 2014), IISc-Bangalore, India, 22-25 July 2014. (IEEE- Xplore)
18. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “A novel architecture for FPGA implementation of Otsu’s global automatic image thresholding algorithm,” in Proceedings of IEEE 27th International Conf. on VLSI Design and 13th International Conf. on Embedded Systems (VLSI Design 2014), Mumbai, India, 5-9 Jan. 2014, pp. 300-305. (IEEE Xplore) [Impact  factor: 0.40]  
19. J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “An FPGA-based novel architecture for the fixed-point binary antilogarithmic computation,” in Proceedings of IEEE International Conf. on Electronic Systems, Signal Processing and Computing Technologies (ICESC), Nagpur, India, 09-11 Jan. 2014, pp. 23-28. (IEEE- Xplore)
20. N. Chaturvedi and S. Gurunarayanan, "An Adaptive Block Pinning Cache for Reducing Network Traffic in Multi-Core Architectures," 2013 5th International Conference and Computational Intelligence and Communication Networks, 2013.
21. N. Chaturvedi, P. Sharma and S. Gurunarayanan, "An adaptive coherence protocol with adaptive cache for multi-core architectures," 2013 International Conference on Advanced Electronic Systems (ICAES), 2013, pp. 197-201, doi: 10.1109/ICAES.2013.6659391.
22. D.C. Kiran, S. Gurunarayanan, J.P.Misra, and D.Yashas "Integrated Scheduling and Register Allocation For Multicore Architecture". In IEEE Conference on Parallel Computing Technologies PARCOMPTECH-2013, Organized by C-DAC in IISC Bangalore, February 2013. https://ieeexplore.ieee.org/document/6621400
23. Munish Bhathia, D.C.Kiran, S Gurunarayanan, and J.P.Misra, "Fine Grain Thread Scheduling on Multicore Processors: Cores With Multiple Functional Units". Compute '13: Proceedings of the 6th ACM India Computing Convention, Vellore, Tamilnadu, India. August 2013 Article No.:20 Pages 1–6
24. D.C. Kiran, S. Gurunarayanan, and J.P.Misra, Compiler Driven Inter Block Parallelism for Multicore Processors. In 6th International Conference on Information Processing, published in the Communications in Computer and Information Science (CCIS), Springer-Verlag, Bangalore, India, August 2012. http://link.springer.com/chapter/10.1007/978-3-642-31686-9_50
25. D.C. Kiran, S. Gurunarayanan, Faizan Khaliq, and Abhijeet Nawal, Compiler Efficient and Power Aware Instruction Level Parallelism for Multicore Architectures. In The International Conference of Eco-friendly Computing and Communication Systems, (ICECCS) 2012, Kochi, India, August 9-11, 2012. Proceedings published in the Communications in Computer and Information Science (CCIS), Springer-Verlag, pp.9-17
26. D.C.Kiran, B. Radheshyam. Gurunarayanan, and J.P.Misra, Compiler Assisted Dynamic Scheduling for Multicore Processors. IEEE Conference on Process Automation, Control and Computing, Coimbatore, Tamilnadu, India, July,20- 22, 2011.  
27. Biju Raveendran, Sundar Balasubramanian, and S. Gurunarayanan. “Evaluation of Priority Based Real Time Scheduling Algorithms: Choices and Tradeoffs.” In Proceedings of the 23rd Annual ACM Symposium on Applied Computing (ACM SAC'08), Brazil, Mar-2008, vol. 1, pp. 302 - 307.
28. Biju Raveendran, T S B Sudarshan, Avinash Patil, Komal Randive, and S Gurunarayanan. “Predictive Placement Scheme for Set-Associative Cache for Energy Efficient Embedded System.” Proceedings of International Conference on Signal Processing, Communications and Networking, (ICSCN 2008), January 4-6, 2008, Chennai, Tamilnadu, India pp. 152-157, Available online in IEEEXPLORE.
29. Biju Raveendran, T S B Sudarshan, Dlip Kumar, Priyanaka Tugudu and S Gurunarayanan. “LLRU: Late LRU Replacement Strategy for Power Efficient Embedded Cache. “Proceedings of 15th IEEE International Conference On Advanced Computing (ADCOM), IIT-Kharagpur, India Dec-2007, pp. 339-344, Available online in IEEEXPLORE.
30. Biju Raveendran, T S B Sudarshan, and S Gurunarayanan. “Selective Placement Data Cache for Low Energy Embedded System”. Proceedings of 14th IEEE International Conference on Advanced Computing (ADCOM), NITK, Surathkal, India. Dec-20-23, 2006, pp. 473-476, Available online in IEE-EXPLORE.
31. Biju Raveendran, T S B Sudarshan, Avinash Patil, Komal Randive, and S Gurunarayanan. “An Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded System.” Proceedings of ESA'07- The 2007 International Conference on Embedded Systems and Applications, USA, (Published by CSREA Press, Jun-2007, pp. 188–194.
32. Biju Raveendran, Sundar Balasubramanian, K Durga Prasad and S. Gurunarayanan. “A Context- Switch Reduction Heuristic for Power-Aware Off-line Scheduling.” 11th Asia-Pacific Computer Systems Architecture Conference (ACSAC), Lecture Notes in Computer Science, Vol. 4186, Springer-Verlag. Shanghai, China, Sep-2006, pp. 404-411.
33. Ninad B Kothari, T S B Sudarshan, S Gurunarayanan, and S Chandrashekhar. “SoC Design of a Low Power Wireless Sensor Network Node for Zigbee Systems.” Proceedings of 14th IEEE International Conference On Advanced Computing (ADCOM), NITK, Surathkal, India.  Dec- 20-23-2006, pp.  462-466. Available online in IEE-EXPLORE.
34. Ninad B Kothari, T S B Sudarshan, Shipra Bhal, Tejesh E C, and S Gurunarayanan. “Design of an Efficient Low-Power AES Engine for Zigbee Systems.” Proceedings of 10th IEEE VLSI Design & Test Symposium (VDAT), Goa, India. Aug-2006, pp. 264-272.
35. S.Gurunarayanan , R Mehrotra and S Chandrashekhar. “Modelling of ESD Protection Circuits. “Proceedings of 8th International Workshop on Physics of Semiconductor Devices, New Delhi, India. 1995.
36. .Gurunarayanan , R Mehrotra and S Chandrashekhar.”Drain Induced Barrier lowering in short channel NMOS Devices.”Proceedings of 7th International Workshop on Physics of Semiconductor Devices. New Delhi, India Dec. 14-18, 1993. 75-76. Narosa Publishing House, 1994