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Dr. Anu Gupta

Professor, Department of EEE, BITS Pilani, Pilani Campus

Mixed Signal VLSI Design, HDL Synthesis and FPGA Architectures, Low Power Analog and Digital Circuits Design, ASIC Design
Department of Electrical and Electronics Engineering, Birla Institute of Technology & Science, Pilani- 333031, Rajasthan. India.

 

Books Review:

  • Microelectronic Devices and Circuits. Tata McGraw-Hill Publishing Company Limited, 2003

Journal/ Conference Reviewer  Panel member :

  • VLSI Design & Test Symposium , 200,    PAPER TITLE: Synthesis Of Multiple-Valued Arithmetic Functions Using         Evolutionary  Process
  • VLSI DESIGN & TEST SYMPOSIUM , 2005     PAPER TITLE: Implementation Of Vedic Mathematics Rules For Fast Multiplication Using Hdl
  • IETE TECHNICAL REVIEW, 2006,    Paper Title: Energy Efficient Charge Recovery For Positive Feedback Adiabatic Logic
  • IETE Technical Review, 2007,     Paper Title: Low Power 8-Bit Data Compression Hardware Using Adiabatic Logic
  • IEEE Potentials, 2007,    Paper Title: Availability Based Tariff-An Introduction
  • IEEE Potentials, 2008 Manuscript Id: Pot-2008-0068,   Paper Title: High Performance Development As Distributed Generation: A New Paradigm For Sustainable Electrical Energy
  • International Joint Conferences On Computer, Information And Systems Sciences And Engineering (Cis2e 08)  2008,    Paper Title:  Engineering & Globalization: Effects On Engineering Practitioners.
  • International Joint Conferences On Computer, Information And Systems Sciences And Engineering   (Cis2e 08)  2008,   Paper Title:  Simulating VHDL In Pspice Software 

Research Paper Review

  • IET, Electronic Letters, Paper Title --' Power-efficient, high-PSNR current mode approximate full adder based on CNTFETs '.
  • IET, Electronic Letters, Paper Title-- A Synchronization Buffer Reduction Technique for Energy and Area Efficient 4-phase Adiabatic Systems
  • IET, Electronic Letters, Paper Title-- Novel Reversible CLA, Optimized RCA, and Parallel Adder/Subtractor Circuits
  • IET, Electronic Letters, Paper Title— OTS Device based Integrate and Fire Neuron in Neural Network for Processing Biological Signals
  • IET, Electronic Letters, Paper Title— Simple CMOS square wave generator with variable mode output
  • IET, Electronic Letters, Paper Title— Asynchronous sampling of an active non-synchronised time-to-digital converter
  • IET, Electronic Letters, Paper Title— Inverter-based sigma-delta modulator based on three-phase clock technique
  • IET, Circuits, Devices & Systems, Paper Title— Computation and Analysis of Excitatory Synapse and Integrate & Fire Neuron: 180nm MOSFET and CNFET Technology
  • IET, Circuits, Devices & Systems, Paper Title --A Novel Energy Efficient adder using CNTFET technology
  • IET, Circuits, Devices & Systems, Paper Title --A novel method for designing ternary adder cell based on CNFETs
  • IET, Circuits, Devices & Systems, Paper Title --A Fast Method for Process Reliability Analysis of CNFET-based Digital Integrated Circuits
  • IET, Circuits, Devices & Systems, Paper Title --Carbon Nanotube FET-based Low-Delay and Low-Power Multidigit Adder Designs
  • IET, Circuits, Devices & Systems, Paper Title --A new approach for designing compressors with a new Hardware-Friendly mathematical method for Multi-input XOR Gates
  • Taylor & Franscis, International Journal of Electronics, Paper Title— Robust Low Power Transmission Gate (TG) based 9T SRAM cell with Isolated Read and Write Operation
  • Taylor & Franscis, International Journal of Electronics, Paper Title-- Design of Improved Domino Logic for Low Leakage Wide Fan-In CNTFET Circuits
  • Taylor & Franscis, International Journal of Electronics, Paper Title-- DPL-Based Novel CMOS 1-Trit Ternary Full-Adder
  • Taylor & Franscis, International Journal of Electronics, Paper Title-- Implementing Three Novel MVL Current Mode Full Adders Using CNTFT
  • Taylor & Franscis, International Journal of Electronics, Paper Title— DPL-Based Novel CMOS 1-Trit Ternary Full-Adder
  • Taylor & Franscis, International Journal of Electronics, Paper Title— Power aware Logic for VLSI Applications
  • Taylor & Franscis, International Journal of Electronics, Paper Title-- Gaussian Distribution Model for Gate to Channel Capacitance

Guided/ Guiding Phd

PhD Ongoing 
 
Name: Abheek Gupta

Area: Artificial Neural Networks algorithms for classification and pattern recognition on digital hardware

Name: Shashi Kant Sharma 
Area :  Energy Efficient Hardware Architectures for Machine Learning Algortihms
 
Name: Buddhi Prakash Sharma
Area:  Low power Analog and mixed signal systems 
PhD  completed
Name-- Snehlata Murotiya   (THESIS DEFENDED  ON 20  AUG 2016 and Awarded)
Proposed Area and topic of Research  --Low Power High Speed and Compact Ternary VLSI Circuit Designs using Carbon Nanotube Field Effect Transistors
 
Name-- Priya Gupta  ( THESIS DEFENDED ON 20 FEB. 2018 and Awarded)
Proposed Area and topic of Research -- Architectural Exploration and Implementation of Low Power Memory & Arithmetic Circuits using Subthreshold Design Techniques
 
 Name--Vineet Kumar  (THESIS DEFENDED  ON 10  March 2017 and awarded)
Proposed Area and topic of Research--Iris Localization in Iris Recognition System: Algorithm and Hardware Implementation
PhD Thesis Examiner
External Thesis Examiner to evaluate Doctoral Thesis , Shiv Nadar University
Thesis entitled “DESIGN AND ANALYSIS OF RELIABILITY-AWARE CMOS CIRCUITS FOR A NEUROMORPHIC  SYSTEM
F Energy Harvester
 
Research interests

RESEARCHER--- For me,research is for , solving the national and local problems. Working with students on a research project is a way to provide chance to inquisitive brain to solve the problems around them using their knowledge.   This also broadens my own horizon, and   gives me new perspective to teach out of the text books.

 Research Areas--

  •  Low power Mixed Signal VLSI Design
  • HDL Synthesis and FPGA Architectures
  • Low Power Analog Circuits Design

Please view  my publication details at    

Dissertation/ Thesis Supervised
  • Undergraduate: over 1500 (Project Courses)
  • Undergraduate: over 30 First Degrees Thesis
  • Graduate: Over 5  (Dissertation)