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Dr. Anu Gupta

Professor, Department of EEE, BITS Pilani, Pilani Campus

Mixed Signal VLSI Design, HDL Synthesis and FPGA Architectures, Low Power Analog and Digital Circuits Design, ASIC Design
Department of Electrical and Electronics Engineering, Birla Institute of Technology & Science, Pilani- 333031, Rajasthan. India.

Journal / Conference Publications

Complete Publications list (Title of paper, authors, Journal details, pages, year etc.):

International Journals

[33]  M. V. Shenoy, S. Sridhar, G. Salaka, A. Gupta and R. Gupta, "A Holistic Framework for Crime Prevention, Response, and Analysis With Emphasis on Women Safety Using Technology and Societal Participation," in IEEE Access, vol. 9, pp. 66188-66207, 2021, doi: 10.1109/ACCESS.2021.3076016.

[32]  Harjap Singh Saini and Anu Gupta, "Constant Power Consumption Design of Novel Differential Logic Gate for Immunity against Differential Power Analysis", IET Circuits Devices Syst. 13(1): 103-109 (Dec.2019) --SCI Indexed, SCI-E, Scopus, IET Inspec , EI Compendex, Impact Factor: 1.308 CiteScore: 1.49. SNIP: 1.014

[31]  Vineet Kumar, Abhijit Asati and Anu Gupta, “Memory-Efficient Architecture of Circle Hough Transform and Its FPGA Implementation for Iris Localization,” IET Image Processing, April 2018, DOI: 10.1049/iet-ipr.2017.1167,Online ISSN 1751-9667), (Impact factor: 1.044) -- SCI Indexed, SCI-E, Scopus, IET Inspec, EI Compendex

[30] Anu Gupta Priya Gupta, and Abhijit Asati, "Novel Low Power and Stable SRAM Cells for Subthreshold operation at 45 nm" International Journal of Electronics, February 2018. (DOI:10.1080/00207217.2018.1440437) --SCI, SCI-E, Scopus,Web of Science Indexed

[29] Vineet Kumar, Abhijit Asati and Anu Gupta,"Low-Latency Median Filter Core for Hardware Implementation of 5-by-5 Median Filtering," IET Image Processing, August 2017, (doi: 10.1049/iet-ipr.2016.0737, impact Factor: 1.044) -- SCI Indexed

[28] Vineet Kumar, Abhijit Asati, Anu Gupta, “Hardware Accelerators for Iris Localization”, Springer Journal of Signal Processing Systems, September 2017. ( DOI 10.1007/s11265-017-1282-2, Impact factor:0.893) -- SCI-E Indexed

[27] Vineet Kumar, Abhijit Asati and Anu Gupta, "Hardware implementation of a novel edge-map generation technique for pupil detection in NIR Images," Elsevier Journal Engineering Science and Technology, an International Journal (JESTEC), November 2016, (DOI information: 10.1016/j.jestch.2016.11.001) -- Scopus Indexed

[26] Vineet Kumar, Abhijit Asati and Anu Gupta, “Accurate iris localization using edge map generation and adaptive circular Hough transform for less constrained infrared iris images,” Int. Journal of Electrical and Computer Engineering, IAES publication, Indonesia, Vol. 6, No.4, pp. 1637-1646, August 2016. (SNIP: 1.090, H index:8) -- Scopus Indexed

[25] Vineet Kumar, Abhijit Asati and Anu Gupta, “A novel edge-map creation approach for highly accurate pupil localization in unconstrained infrared iris images”, Journal of Electrical and Computer Engineering, Hindawi publishing corporation Vol. 2016, Article ID 4709876, May 2016. (http://dx.doi.org/10.1155/2016/4709876) (H index:14) -- Scopus Indexed

[23] S. L. Murotiya and Anu Gupta, “Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology,” International. Jounal of Electronics, Taylor & Francis, Sep. 2015. DOI:10.1080/00207217.2015.1082199 , SCI Indexed, (IMPACT FACTOR-0.459)

[20] Priya Gupta, Anu Gupta and Abhijit Asati "Power-Aware Design of Logarithmic Prefix Adders in Subthreshold Regime: A Comparative Analysis" Elsevier journal of Procedia Computer Science, Vol. 46, pp. 1401 – 1408, 2015.

[19] Snehlata Murotiya, Anu Gupta “Design of hardware efficient low power 2-bit Ternary ALU using CNTFETs”, International Journal of Electronics, Taylor & Francis, 2015, http://dx.doi.org/10.1080/00207217.2015.1082199 , SCI Indexed, (IMPACT FACTOR-0.459)

[18] Sneh Lata Murotiya and Anu gupta (2014), “A Novel Design of Ternary Full Adder using CNTFETs” Arabian Journal of Science and Engineering ,DOI 10.1007/s13369-014-1350-x, Springer, 2014 SCI Indexed, (IMPACT FACTOR-0.367)

[15] Sneh lata Murotiya and Anu gupta (2014), "Design of content-addressable memory cell using CNTFETs", International Journal of Electronics Letters ,Taylor & Francis, 2014 DOI: 10.1080/21681724.2014.911368 , SCI Indexed, , (IMPACT FACTOR-0.751)

[14] Sneh Lata Murotiya and Anu gupta (2013), “Design of CNTFET-based Radiation hardened Latches” European Journal of Scientific Research, Scientific Research Platform , Volume 117 Issue 1, 2013. (IMPACT FACTOR-0.713)

[13] Sneh lata Murotiya and Anu gupta (2013), " Design of CNTFET based 2-bit ternary ALU for nano-electronics, International Journal of Electronics, Taylor & F.rancis, 2013, DOI: 10.1080/00207217.2013.828. SCI Indexed, (IMPACT FACTOR-0.751)

[7] S. K. Sahoo, Anu Gupta, Abhijit R. Asati and Chandra Shekhar “A Novel Redundant Binary Number to Natural Binary Number Converter” Journal of Signal Processing Systems (Springer), Vol. 59, 2010, pp: 297-307(IMPACT FACTOR --0.551)

[5] S K Sahoo, Chandra Shekhar, Sudeepti Kodali, Abhijit R. Asati and Anu Gupta, “Dual Channel Addition Based FFT Processor Architecture for Signal and Image Processing” , Int. J. High Performance Systems Architecture, Vol. 2, No. 1, 2009, pp-35-45.

[3] Nikhil Bhattar, Anu Gupta, “On-chip resistors can make a stable current reference”, Potentials, IEEE, Volume: 27, Issue: 1, 2008, pp-31-36, SCI INDEXED , (Impact Factor-- 4.934)

[2]  Anu Gupta, Bipin Naraynan Kulkarni, “Automation of Clock Distribution Network Design for Digital Integrated Circuits using Divide and Conquer technique” , Integration, the VLSI Journal, Vol. 39, issue 4, pp 407-419, ELSEVIER, 2006, pp-407-419. SCI Indexed, (IMPACT FACTOR --0.66)

40.  Anu Gupta, Chandra Shekhar, “Performance exploration of adder architectures for small to moderate-sized low power, high performance adders” , Journal of Microelectronics International, Emerald Publishing, Vol. 22 No. 3, 2005, pp-20-27 , Scopus Indexed, (IMPACT FACTOR --0.73)

41.  Anu Gupta, & Ganesh TS, “A Comparison of Adiabatic Logic Circuit Techniques for an Energy Efficient 1-bit Full Adder Design”, Journal of Research, IETE, Taylor and Franscis, Volume 50, No. 1, Jan.-Feb. 2004, pp-29 – 36 . . (IMPACT FACTOR-0.2)

National Conferences

1.  Anu Gupta, & Chandrashekhar, “Adder Architectures for fully static and complementary pass logic designs” , Proceedings of the national seminar on VLSI: Systems, Design and Technology, IIT Bombay, Dec. 10-11, 2000, pp-140-145

2. Anu Gupta, & Chandrashekhar, “Design Exploration of Architecture for Optimal Adder Synthesis”, IETE Golden Jubilee Seminar on Electronic Design Automation: Issues and Challenges, April 26, 2003, pp-4-6
3. S K Sahoo, Chandra Shekhar, Anu Gupta, “A Compact Fast Parallel Multiplier Using Modified Equivalent Binary Conversion Algorithm”, Proceedings of VLSI Design and Test Workshop , Aug. 26-28, 2004

4. Arpit Kumar Gupta, Anu Gupta, “A Design Methodology for Efficient Design of fully differential OP AMP as a Voltage Buffer.”, IMS Conference-2006, Electronics Science Department, Kurukshetra university, Kurukshetra, February 17-18, 2006. 

5. Anu Gupta, Ninad B Kothari, “Effect of Transistor Sizing in Design of an Energy Efficient 1-bit Full Adder Design using different Adiabatic Logic Circuit Techniques”, IMS Conference-2006, Electronics Science Department, Kurukshetra university, Kurukshetra, February 17-18, 2006

7. Sameer Somvanshi , S C Bose, Anu Gupta, “A novel sub-1 Volt Bandgap Reference with all CMOS”, Proceedings of the 12th WSEAS international conference on Circuits, Heraklion, Greece. World Scientific and Engineering Academy and Society Year of Publication, 2008 , pp-232-237

9. Gaurav Agarwal, Amit Singhal, Anu Gupta, Prayush Kumar, “Hardware Implementation of Delighting Module for Using it in a Digital Camera Chip”, Proceeding Of 13th IEEE VLSI Design And Test Symposium held on July 8-10, 2009, Bangalore, pp-96-104

10. Raj Dua, Sumeet Tiwana, Anu Gupta, “Ultra Low Power Digital to Analog Converter “,Progress In VLSI Design And Test 2009, Proceeding Of 13th IEEE VLSI Design And Test Symposium held on July 8-10, 2009, Bangalore, pp-271-279

11. Raj Singh Dua, Anu Gupta, “A Novel Ultra Low Power Current Mirror Circuit for Biasing Operational Amplifier in Sub-threshold Region for Virtual Instrumentation Systems”, National Conference On Virtual And Intelligent Instrumentation( NCVII-09), 13-14 Nov. 2009, BITS, Pilani , Rajasthan (best paper award)

12. Hariprasad Chandrakumar , Anu Gupta, “A Micropower Low-noise CMOS Neural Amplifier for Bio-medical Instrumentation”, National Conference On Virtual And Intelligent Instrumentation( NCVII-09), 13-14 Nov. 2009, BITS, Pilani , Rajasthan

13. Amit Agarkhed, Sharvil Patil, Anu Gupta, “Improved Implementation of CRL and SCRL Gates for Ultra-Low Power”, International conference on advances in recent technologies in communication and comutind, ARTCOM 2009, Technically Co-sponsored by the IEEE-Computational Intelligence Society, Kottayam, Kerala India., 27 - 28 Oct 2009 (paper is archived in the IEEE Xplore) Archived in IEEE EXPLORE (Impact Factor-- 4.934)

14. Sneh Lata Murotiya and Anu Gupta, “An Exploration of VLSI parallel Adder using Carbon NanoTube Field Effect Transistor,” Souvenir of National Conference on VLSI Design and Embedded Systems, CEERI, Pilani, pp-7A.5, October 12-14, 2011

15. Anu Gupta and Subhrojyoti Sarkar, “An Efficient High Frequency and Low Power Analog Multiplier in Current Domain,” Proceedings of 16th International Symposium, pp-1-9, VDAT 2012, Shibpur, India, July 1-4, 2012

16. Sivaram Prasad Kopparthy, Ishit Makwana, Anu Gupta, “Asynchronous 8-bit Pipelined ADC for Self-Triggered Sensor based Applications”, Asia-Pacific Conference on Postgraduate Research in Microelectronics & Electronics (Prime Asia), Dec 5-7, 2012, BITS-Pilani, Hyderabad Campus (paper is archived in the IEEE Xplore) (IMPACT FACTOR-4.934)

17. Sneh Lata Murotiya, Aravind Matta and Anu Gupta, “Performance evaluation of CNTFET based SRAM cell design.” Proc. of Inter National Conference on Electrical Engineering and Computer Science,”, May 12, 2012, Trivandrum, Kerala, pp-88-92

18. Sivaram Prasad Kopparthy, Ishit Makwana, Anu Gupta, “An Asynchronous 8-bit 5 MS/s Pipelined ADC , Jan 17-19, 2013, World Trade Center, Bangalore, India (paper is archived in the IEEE Xplore) (IMPACT FACTOR-4.934)

International Conferences (India)

  1. Tushar Uttarwar, Sanket Jain, Anu Gupta, “Design of a High Performance, Low Power, Fully Differential Telescopic Amplifier using Stable Common-Mode Feedback Circuit”, International Joint Conferences on Computer, Information and Systems Sciences and Engineering, December 5th – 13th, 2008, Sponsored by University of Bridgeport, Technically co-sponsored by IEEE Computer Society and Communications Society
  2. Ashutosh Mehra, Anu Gupta, Sharvil Patil, Abhishek Mehra, “A Novel Dynamic Current Boosting Technique for Enhancement of Settling Time and Elimination of Slewing of CMOS Amplifiers”, International conference on advances in recent technologies in communication and computing, ARTCOM 2009, Technically Co-sponsored by the IEEE-Computational Intelligence Society, Kottayam, Kerala India., 27 - 28 Oct 2009 (paper is archived in the IEEE Xplore) (IMPACT FACTOR-4.934)
  3. Vivek Gupta, Anu Gupta, Nitin Chaturvedi, Abhijit Asati, “A Novel Technique for Improvement of Power Supply Rejection Ratio in Amplifer Circuits “, International Conference on Advances in Computing, Control, & Telecommunication Technologies, 2009. ACT '09. December 28-29, 2009, Trivandrum, Kerala, India (paper is archived in the IEEE Xplore), pp-756 – 758 . (IMPACT FACTOR-4.934)
  4. Maneesh Menon, Karan Dhall, Anu Gupta, Nitin Chaturvedi , “High bandwidth Low Power Cascaded Three Stage Amplifier with Multi-path Nested Miller Compensation for high performance IC Applications”, International Conference on Recent Trends in Information, Telecommunication and Computing – ITC 2010, March 12-13, 2010 in Kochi, Kerala, India, Paper is archived in the IEEE Xplore, pp-9 – 12. (IMPACT FACTOR-4.934)
  5. Anu Gupta, Jithin P. Thomas, K.R.S.N. Kumar, Vamsidhar Addanki, Nitin Chaturvedi, “Hardware Implementation of a biometric fingerprint Identification System”, International Joint Journal Conference in Computer, Electronics and Electrical, CEE 2010
  6. Gaurav Jain,Vaibhav Gogte, Shivani Bathla, Anu Gupta, “An Exploration of Efficient Architecture for Double Data Rate SDRAM for a High Performance Implementation, International Conference on Advances in Electrical & Electronics (AEE), Dec 20-21, 2011 in Noida, India
  7. Himadri Raghav, Sachin Maheshwari, Anu Gupta, “A Comparative Analysis of Power & Delay Optimize Digital Logic Families for High Performance System Design", International Conference on Electronic Systems (ICES 2011), NIT Rourkela
  8. Anu Gupta, Mohammad Waqar Ahamed, Abhishek Dhir , Ravish Soni, Neeraj Kumar Sharma, “ Novel Method To Implement High Frequency All Digital Phase-Locked Loop On FPGA”, International Conference on VLSI & Communication Systems , SAINTGITS College of Engineering, Pathamuttom, Kotyam, Kerala, 2011
  9. Gaurav Jain, Vaibhav Gogte, Shivani Bathla, Anu Gupta, “An Exploration of Efficient Architecture for Double Data Rate SDRAM for a High Performance Implementation, “International Conference on Advances in Electrical & Electronics (AEE), Noida, India , Dec 20-21 2011, Paper ID-AET_AEE_507
  10. Sachin Maheshwari, Amitoj Singh and Dr. Anu Gupta, "Design of Logical Effort for Worst Case Power Estimation in a CMOS Circuit in 90 nm Technology", Proc. of the Int. Conf. on Advances in Computer, Electronics and Electrical Engineering (ICACEEE-2012), March 25-27, Mumbai, pp. 91-95, 2012. (ISBN: 978-981-07-1847-3). (Also published in UACEE International Journal of Advances in Electronics Engineering, Vol. 2, Issue 2, pp. 39-43, ISSN 2278 - 215X [Online]
  11. Sneh Lata Murotiya, Aravind Matta, Anu Gupta, “Performance evaluation of CNTFET based SRAM cell design.” Proc.of International Conference on Electrical Engineering and Computer Science,” pp-88-92, May 12, 2012, Trivandrum, Kerala
  12. Sachin Maheshwari, Rameez Raza, Pramod Kumar and Dr. Anu Gupta, " Convex Optimization of Energy and Delay using Logical Effort Method in Deep Sub-Micron Technology" Proc. of the 17th International Symposium on VLSI Design and Test (VDAT 2013), July 27-30, Malaviya National Institute of Technology (MNIT), Jaipur, India, 2013.
  13. Sachin Maheshwari, Himadri Singh Raghav and Dr. Anu Gupta, " Characterization of Logical Effort for Improved Delay" Proc. of the 17th International Symposium on VLSI Design and Test (VDAT 2013), July 27-30, Malaviya National Institute of Technology (MNIT) Jaipur, India, 2013.
  14. Priya Gupta, Anu Gupta and Abhijit Asati “A Review on Ultra Low Power Design Technique: Sub-threshold Logic ” International Journal of Computer Science and Technology-IJCST,Vol.4, Issue Spl-2, April-June , 2013, ISSN: 0976-8491 (Online) ISSN : 2229-4333 (Print)
  15. Sachin Maheshwari, Himadri Singh Raghav and Dr. Anu Gupta, " Characterization of Logical Effort for Improved Delay" VLSI Design and Test, Communications in Computer and Information Science, Vol. 382, pp. 108–117, 2013. (© Springer-Verlag Berlin Heidelberg 2013).
  16. Sachin Maheshwari, Rameez Raza, Pramod Kumar and Dr. Anu Gupta, "Convex Optimization of Energy and Delay using Logical Effort Method in Deep Sub-Micron Technology" VLSI Design and Test, Communications in Computer and Information Science, Vol. 382, pp. 185–193, 2013. (© Springer-Verlag Berlin Heidelberg, 2013
  17. Sneh Lata Murotiya, Anu Gupta, "CNTFET Based Design of Content Addressable Memory Cells", 4th IEEE International Conference on Computer and Communication Technology (ICCCT – 2013), MNNIT Allahabad, pp.1-4, Sep.20-22, 2013. Paper is archived in the IEEE Xplore,. (IMPACT FACTOR-4.934)
  18. Sneh Lata Murotiya, Anu Gupta, “Performance Evaluation of CNTFET based Dynamic Dual Edge Triggered Register”, 1st IEEE International Conference on Advanced Electronic Systems (ICAES – 2013), CEERI Pilani, pp. 180-183, Sep. 21-23, 2013. . Paper is archived in the IEEE Xplore,. (IMPACT FACTOR-4.934)
  19. Sneh Lata Murotiya, Anu Gupta, “DESIGN AND ANALYSIS OF CNTFET BASED D FLIP-FLOP”, presented in ICCS – 2013, BKBIET Pilani and published in IJECET, vol.4, issue 7 pp. 144-149, 2013.
  20. Sneh Lata Murotiya, Anu Gupta, “Performance Evaluation of CNTFET based DTCAM cell”, IEEE Conference INDICON – 2013, IIT Mumbai. Paper is archived in the IEEE Xplore,. (IMPACT FACTOR-4.934)
  21. Priya Gupta, Akshay Kumar Sharma, Pratishtha Dehadray, Anu Gupta “Design and Implementation of low power TG Full Adder design in subthreshold regime” IEEE International Conference on Intelligent Interactive Systems and Assistive Technologies, August 2-3, 2013, Coimbatore, INDIA. Paper archived in the IEEE Xplore,. (IMPACT FACTOR-4.934)
  22. Priya Gupta, Ishan Munje, Nikhil Kaswan , Anu Gupta , Abhijit Asati “Analysis & Implementation of Ultra Low-Power 4-bit CLA in subthreshold regime” Selected to be published on IEEE International Conference on Circuit, Power and Computing Technologies” (ICCPCT), March 20th-21st 2014, Tamilnadu . Research Institute, Pilani, September 21-23, 2013 Paper archived in the IEEE Xplore,. (IMPACT FACTOR-4.934)
  23. Nikhil Kaswan , Ishan Munje, Yash Kothari , Priya Gupta, Anu Gupta “Implementation of high speed energy efficient 4-bit binary CLA based incrementer /decrementer” in 2013 International Conference on Advanced Electronic Systems (ICAES), Sept. 21-23 2013, CEERI Pilani. Paper is archived in the IEEE Xplore,. (IMPACT FACTOR-4.934)

  24. Abhilash K N, Shakthi Bose, Anu Gupta, " Abhilash K N, Shakthi Bose, Anu Gupta, " A High Gain, High CMRR Two-Stage Fully Differential Amplifier Using gm/Id technique for Bio-medical Applications", IEEE PrimeAsia 2013 Conference held at GITAM University, Visakhapatnam Campus, 19th -21st December 2013. Paper is archived in the IEEE Xplore,. (IMPACT FACTOR-4.934)

  25. Siddharth Malhotra , Abhinav Mishra, Rakesh B R , Anu Gupta, "Frequency Compensation in Two-Stage Operational Amplifiers for Achieving High 3-dB Bandwidth” IEEE PrimeAsia 2013 Conference held at GITAM University, Visakhapatnam Campus, 19th -21st December 2013. Paper is archived in the IEEE Xplore (IMPACT FACTOR-4.934)

     

  26. Ganesh Raj, Ankur Gupta , Dr. Anu Gupta, " Self timed High speed 8-bit SAR ADC in 0.35um", IEEE Conference INDICON – 2013, IIT Mumbai . Paper is archived in the IEEE Xplore (IMPACT FACTOR-4.934) DOI: 10.1109/INDCON.2013.6726028

     

  27. Jaskaran Singh Grover , Anu Gupta ,"Studying Crosstalk Trends for Signal Integrity on Interconnects using Finite Element Modeling", COMSOL Conference 2013 October 17 - 18, 2013, Bangalore

International Conferences (Abroad)

  1. Cherin Joseph, Anu Gupta, “A novel hardware efficient Digital Neural Network architecture implemented in 130nm technology”, The 2nd International Conference on Computer and Automation Engineering (ICCAE), 2010, Paper is archived in the IEEE Xplore, pp-82-87 (IMPACT FACTOR-4.934)
  2. Priya Gupta, Ishan Munje, Nikhil Kaswan, Anu Gupta and Abhijit Asati, “Analysis & Implementation of Ultra Low-Power 4-bit CLA in subthreshold regime” IEEE International Conference on Circuit, Power and Computing Technologies” (ICCPCT), 20-21 March 2014, Tamilnadu.
  3. Priya Gupta, Anu Gupta and Abhijit Asati, "Power-Aware Design of Logarithmic Prefix Adders in Sub-Threshold Regime: A Comparative Analysis" International Conference on Information and Communication Technologies (Under TEQIP Phase-II)-ICICT, 3-5 December 2014, Kochi.
  4. Snehlata Murotiya, Anu Gupta , Sparsh Vashishtha " Novel Design of Ternary Magnitude Comparator using CNTFETs", 11th IEEE India Conference, INDICON-2014, 11-13th dec. 2014, Yashada, Pune
  5. Vineet Kumar, Abhijit Asati, Anu Gupta, “An Iris Localization Method for Noisy Infrared Iris Images" IEEE International Conference on Signal and Image Processing Applications (ICSIPA) Kuala Lumpur, Malaysia, 18-21 October, 2015.
  6. Priya Gupta, Divya Samnani, Anu Gupta, Abhijit Asati, "Design and ASIC Implementation of Column Compression Wallace/Dadda Multiplier in Sub-Threshold Regime," Proceedings of the 9th INDIACom;INDIACom - 2015, 2nd International Conference on “Computing for Sustainable Global Development”, New Delhi, India, 11– 13 March, 2015.
  7. Priya Gupta, Ishan Munje, Nikhil Kaswan, Anu Gupta and Abhijit Asati, “Effectiveness of body bias & hybrid logic: An energy efficient approach to design adders in sub-threshold regime” International Jounal. of Circuits and Architecture, Design -Inderscience Publishers, 2015)
  8. Deepansh Dubey, Anu Gupta: A Low Power Low Noise Bio-Amplifier with Tunable Gain, IEEE International Conference on Electrical, Computer and Communication Technologies (EESCO 2015), VIIT, Vishakhapatnam, 24th-25th January 2015.
  9. D. Dubey, Anu Gupta, "A Low Power Low Noise Amplifier for Biomedical Applications", Electrical, Computer and Communication Technologies (ICECCT), 2015 IEEE International Conference on , 5-7 March 2015, SVS College of Engineering, Coimbatore, pp:1-6, DOI:10.1109/ICECCT.2015.7226134 , Paper is archived in the IEEE Xplore,. (IMPACT FACTOR-4.935)
  10. D. Dubey, Anu Gupta ,"Improvement of Operational Amplifier in Subthreshold Region using Forward Body Bias", IEEE India Conference (INDICON), Jamia Millia Islamia, New Delhi, India from 17-20 December 2015 Paper archived in the IEEE Xplore,. Paper is archived in the IEEE Xplore, pp-82-87 (IMPACT FACTOR-4.934)
  11. Priya Gupta, Anu Gupta and Abhijit Asati, “Ultra Low Power MUX Based Compressors for Wallace and Dadda Multipliers in Sub-Threshold Regime” American Journal of Engineering and Applied Sciences, Nov. 2015, pp:702-716,DOI: 10.3844/ajeassp.2015.702.716
  12. V. Kumar, A. Asati, and A. Gupta, “Iris Localization Based on Integro-Differential Operator for Unconstrained Infrared Iris Images”, International Conference on Signal Processing, Computing and Control, JUIT, Waknaghat, India, Sept. 2015.
  13. V. Kumar, A. Asati, and A. Gupta, “An Iris Localization Method for Noisy Infrared Iris Images”, IEEE International Conference on Signal and Image Processing Applications, Kuala Lumpur, Malaysia, Oct. 2015.
  14. Rajiv Gupta, Leela Krishna Kondepati, Anu Gupta, " Tender Evaluation by Visual Decision Support System", IIE and URUAE International Conference, March 20-21, 2016 Mauritius
  15. Rajiv Gupta, Anu Gupta, Advait Nair, "To predict the impact of passive architecture on the temperature conditions inside a building using ANN" , The 7th International renewable Energy Congress, March 22 – 24, 2016, Hammamet, Tunisia, SCOPUS indexed.
  16. Karan Raj Singh, Anu Gupta,"A Hardware optimized Low power RNM Compensated three stage Operational amplifier with Embedded Capacitance Multiplier Compensation" 2nd IEEE International Conference on VLSI Systems, Architecture, Technologies and Applications (VLSI SATA 2016), Amrita School of Engineering, Bengaluru, India, 10 - 12 January 2016 , Paper in the IEEE Xplore DOI: 10.1109/VLSI-SATA.2016.7593038,Scopus indexed.
  17. Priyesh Shukla, Anu Gupta, "Quad-NMOS Cross-coupling for Linearity Enhancement in High Frequency Continuous-time OTA-C Filters with IM3 Below -70 dB", 6th International Conference on Information and Electronics Engineering (ICIEE 2017), February 22-24, 2017, Singapore, Scopus indexed
  18. Priyesh Shukla, Anu Gupta, "Current-Mode PMOS Capacitance Multiplier", International Conference on Inventive Systems and Control (ICISC 2017) ,19-20 January 2017 , JCT College of Engineering and Technology, Coimbatore, IEEE sponsored, Scopus indexed
  19. Prakhar kumar, Srijan Rastogi, and AnuGupta, "Novel design of linear low power Gm-C based voltage controlled filter with programmable gain", International Conference Of Science Technology & Management (ICSTM-2017), 24 september 2017, Bengaluru.
  20. Brahmbhatt Viralkumar Kishorkumar, AnuGupta ,"Demonstration of CORDIC based Digitally assisted analog using 12 bit pipelined ADC ", International Conference Of Science Technology & Management (ICSTM-2017), 24 september 2017, Bengaluru.
  21. Abheek Gupta, Anu Gupta, and Rajiv Gupta, " Power and Area Efficient Intelligent Hardware Design for Water Quality Applications", 1st International Conference on on Microelectronic Devices and Technologies (MicDAT '2018) 20-22 June 2018, Barcelona, Spain
  22. Kalpraj Vaidya , Anu Gupta, and Rajiv Gupta, "High Gain, High Bandwidth Fully Differential low voltage OpAmp Design Using Self-Cascode MOSFET with Adaptive Bias and Common mode Feedback", 1st International Conference on on Microelectronic Devices and Technologies (MicDAT '2018) 20-22 June 2018, Barcelona, Spain
  23. Harjap Singh Saini, Anu Gupta, “Differential Power Analysis Immune Design of FinFET Based Novel Differential Logic Gate” . 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 26-29 May 2019. DOI: 10.1109/ISCAS.2019.8702598
  24. Gupta R, Rastogi, A , Sheno, M V, Sridhar, S, Gupta A, “ Quantitative Analysis of Crime using GIS for Crime against women”, 6th World Conference on Women’s Studies (WCWS 2020), 27th-28th July, 2020.
  25. A. K. Bera, P. Sharma and A. Gupta, "On-Chip Intelligent Frequency Scaling using Artificial Neural Networks," 2020 IEEE 17th India Council International Conference (INDICON), 2020, pp. 1-7, doi: 10.1109/INDICON49873.2020.9342296.