Institutional contribution: 

• 2025: SPOC for M. Tech. VLSI design and Microelectronics curriculum reviewing and revamping  (revised entire ME Microelectronics program chart and curriculum by introducing 18 new courses with benchmarking with renowned Indian and foreign universities, Also got it approved through cross campus faculties, committee and AGC  and Senate. 
• 2025: Introduced a new course Verification Test and Testability of VLSI circuits. 
• 2025: Introduced a new course SOC test and Power Aware Testing
• 2025: Involved as a DLSC member in shortlisting and AV round February-March 2025.
• 2025: Faculty in-charge Srikant Visweswariah Analog Design held in APOGEE-2025
• 2024: Performed squad duty on 13 Dec. 2024 comprehensive examinations
• 2024: In-charge of OLAB since 4 September 2024
• 2024: Involved as a DLSC member coordinate the shortlisting process for candidates in the Microelectronics and Embedded system, November 2024.
• 2024: Interacted with the Micron Singapore team for the international placement of students of Microelectronics students on 24 December 2024.
• 2024: VLSI subject expert for interviews faculty recruitment at BKBIET Pilani on 5 October 2024.
• 2019-2021: Member of Doctoral Counselling  Committee (DCC) of the institute
• Sept 2020: Prepared standard operating procedures for research activities for EEE department 
• 2016 - Feb. 2021: DRC Convener, EEE Department, BITS, Pilani (5 Years).
• 2012 to August 2022: Member DRC, EEE Department, BITS, Pilani (10 Years).
• 2018 to present: Presently member of senate since July 2018.
• 2018 to present: Departmental Level Shortlisting Committee (DLSC) for faculty recruitment since July 2018.
• 2019: Expert for EEE ASTP L-11 selection committee meeting held on 30th September, and 1st October, 2019 at BITS, Pilani. 
• 2012-2017: Academic Program Committee for MS Microelectronics and embedded system programmes.
• 2002-2014: Nucleus member DLPD/WILP.Involved in  DLPD/WILP regular comprehensive exams/ Mid-semester test invigilation duties every semester, conduction WILP viva-voce  examination every semester. WILP dissertation ME thesis-evaluation every semester, Evaluation of PS-II Reports, Conducting examinations outstations.
• 2021: Involved in KHDA moderation process of Dubai campus for CAD for IC Design MEL G641
• 2020: Involved in KHDA moderation process of Dubai campus for CAD for IC Design MEL G641
• 2018: Involved in KHDA moderation process of Dubai campus for electrical Science EEE F111.
• 2021: Panel chair for Ph.D. admission first semester 2021-22
• 2018: Involved in interviews of International students admission
• 2016: Team member for question paper preparation for BITS HD Admission Test
• 2016: Team member for Modifying the Syllabus for BITS HD Admission Test
• 2013: Member of team for the Convocation-2013  held at BITS, Pilani.
• 2012: Visit to UGC Delhi for official work related to project as assigned by Institute.
• 2010-2012: Member of Senate of the institute " Birla Institute of Technology and Science" .
• 2008: Library Committee member for BITS Library from December 2008- December 2009.
• 2007: Team member for question paper preparation for BITS HD Admission Test
• 2006: Executive committee member for Recreational Activity Forum (RAF) from January 2006-December 2007.
• Involved every semester in faculty research proposal evaluation, selection committee member in JRF of sponsored projects, qualifying examination question paper preparation, NAAC report preparation, IoE review data etc.
• ARCD’s registration duties (beginning each semester), campus mid semester & comprehensive exam invigilation, ME Higher degree interview committee member (every semester), involvement in APOGEE paper presentation evaluation

Other Departmental contribution:  

• 2012-2015: Professor in-charge EEE association.
• 2014:2020: Placement Faculty Coordinator (PFAC) , EEE Department, BITS, Pilani. (Conducted a placement lecture session for final year students  e.g. 11/1/2014,  Meeting with industry recruitment personnel)
• 2012:2017: In-charge of OLAB ( Update of CAD tools)

 Participated in conducting BITSAT  FDT/HDT:

 [1] May 2010 to June 2010: Nagpur, Ramdeobaba College of Engineering

 [2] May 2009 to June 2009: Nagpur, Ramdeobaba College of Engineering

[3] 22 June 2024 to 29 June 2024: BITSAT session-2 iON Digital  Zone, IDZ3, Wadi, Nagpur

[4] 25 May 2025 to 30 May 2025: BITSAT session-1, Nagpur (MKH Sancheti Public School, Besa)

[5] 22 June 2025 to 26 June 2025: BITSAT session-2, Indore (iON Digital zone Aurobindo,  Malwa Institute of Science and Technology)

 Participated in HD Admission Test:

• 2016: Team member for Modifying the Syllabus for BITS HD Admission Test
• 2007: Team member for question paper preparation for BITS HD Admission Test
• 2016: Team member for question paper preparation for BITS HD Admission Test

WILP:

• 2024: Participated as subject expert in a workshop for M.Tech. VLSI Design and Microelectronics for handout preparation for new proposed courses, 24-25 November 2024.
• 2023-24: Mentor and Examiner for ESZG628 T Dissertation  (4 students)
• 2022-2023: Mentor and Examiner for ESZG628 T Dissertation  (7 students)
• 2021-2022: Mentor and Examiner for ESZG628 T Dissertation  (15 students)
• 2020-2021: Mentor and Examiner for ESZG628 T Dissertation  (16 students), Reviewed old WILP Question paper for MEL ZG641 CAD for IC Design
• 2019-2020: Mentor and Examiner for ESZG628 T Dissertation  (5 students)
• 2018-2019: Mentor and Examiner for ESZG628 T Dissertation  (4 students)
• 2017: Visited Delhi as Subject expert for WILP guest faculty interview in Microelectronics and Embedded system area on 4, Nov. 2017.
• 2016: 6 August & 7 August  Visited Delhi for WILP Guest Faculty Recruitment
• 2016: Visited Bangalore as Subject expert for WILP guest faculty interview in Microelectronics and Embedded system area on 16-18 August 2016.
• 2013: Conducted WILP B.S. (Power Engineering) and B.S. (Process Engineering) comprehensive examinations held at Gujrat Cement Works, Amreli (Bhawnagar), Gujarat from 18/12/2013 to 23/12/2013.
• 2013: Conducted WILP regular comprehensive exams held at Mahindra & Mahindra Nagpur from 29/6/2013 to 30/6/2013.
• 2012: Online conduction of WILP mid semester examination. (Involved in collecting course section and sub sections to convert WILP mid semester test into online examination, prepared department wise list of all courses and collected information for each course. Also got reviewed handouts of  MS microelectronics program  from expert faculty member to send suggestion for modification needed in course content. Involved in survey of unstructured microelectronics programmes)
• 2012: Got reviewed WILP M.S. Microelectronics program handout from faculty members having area of expertise to suggest if any kind of modification needed in course content as per Bulletin 2010-11.
• 2012: Conducted  WILP regular comprehensive exams held at L&T from 18/7/2012 to 23/7/2012 at Mysore.
• March 2012: Visited Rajasthan Atomic Power Station (RASP) Rawatbhata to identify  the activities of the department, the learning opportunities that can be explored during orientation program of PS-I course, 2012.
• Conducted WILP NTPC comprehensive examination (6 Times) at Koraba, also involved in NTPC thesis evaluation at Korba

Industry Engagement: 

• 2002 to present: Involved as PS-1 instructor (10 times) (For details refer Link:   https://www.bits-pilani.ac.in/Pilani/abhijitasati/Courses)
• May 2014 to July 2014  at "Cypress Semiconductor Limited, Bangalore".

Discussed the VLSI design  and verification process at industry during my visit. 

PS-1 Course Instructor (BITS C221):

[10]  30 May 2023 to 21 July 2023:

CEERI Pilani (Onsite) 

[9]  18 May 2020 to 27 June 2020:

CEERI Pilani (Online) 

Electrono Solutions (Online)

Pyrotech Electronics Udaipur (Online)

[8] 19 May 2019 to 15 July 2019:

 Nagpur (Geomitra Solutions)

 Tirora, (Adani Power Ltd.)-

[7] 21 May 2016 to 18 July 2016:

 Nagpur (GlobalLogic)

 Tirora, (Adani Power Ltd.)-

 [6] 10 May 2015 to 18 July 2015:

 Nagpur (GlobalLogic)

 Tirora, (Adani Power Ltd.)-

 [5] 20 May 2013 to 15 July 2013:

 Nagpur (GlobalLogic, Windals Precision, NEERI, Metalfab Hightech Pvt Ltd.)

 Awarpur (Awarpur Cement Works)  

 [4] 19 May 2012 to 15 July 2012: Nagpur (GlobalLogic, Windals Precision)

 [3] 21 May 2011 to 17 July 2011: RAPS, Rawatbhata

 [2] 22 May 2007 to 18 July 2007: SPM Ltd. Sirpur, Kagaznagar.

 [1] 20 May 2002 to 17 July 2002: SPB Ltd. Erode.

Industry Visits & Collaboration: 

  * Guided a part time Ph.D.  candidate from Semiconductor Industry

• 2018: Opened a PS-1 station at SeeTech, Nagpur for 10 students as a urgent need.
• March 2012: Visited Rajasthan Atomic Power Station (RASP) Rawatbhata to identify  the activities of the department, the learning opportunities that can be explored during orientation program of PS-I course, 2012.

PS-II:

• 2018: Visited PS-II station at Udaipur as required by PS division 30/9/2018 to 2/10/ 2018.
• 2015: Involved as resource person in orientation of PS-II students for VLSI and Electronics companies
• 2012: Visited Bangalore from 24/03/2012 to 28/03/2012  for PS-II students progress evaluation.
• 2012: Initiated the talk to open PS-II station at Global Logic, Nagpur, NEERI, Metalfab Hightech Pvt. Ltd., Nagpur.
• 2010: Visited at Delhi to evaluate the progress of students at PS-II station at ST Microelectronics   (Greater Noida), ST Ericsson (Greater Noida) and Sukam Power systems, Delhi

Summary of PS and BITSAT: