International Journals:

1. Samala, J., Mekala, B.B. & Soumya J. Enhancing fault-tolerant application mapping in network-on-chip through transformer network based reinforcement learning approach. Discov Computing 28, 235 (2025). https://doi.org/10.1007/s10791-025-09704-0

2. Jitesh Choudhary, Chitrapu Sai Sudarsan, Soumya J., A performance-centric ML-based multi-application mapping technique for regular Network-on-Chip, Memories - Materials, Devices, Circuits and Systems,Volume 4, 2023, 100059, ISSN 2773-0646, https://doi.org/10.1016/j.memori.2023.100059. 
3. Jagadeesh Samala, P. Veda Bhanu, Soumya J., Lingareddi C, Reinforcement Learning based Fault-Tolerant Routing Algorithm for Mesh based NoC and its FPGA Implementation, IEEE Access, 9,44724-44737 (2022), - https://doi.org/10.1109/ACCESS.2022.3168992
4. Jagadeesh Samala, P. Veda Bhanu, Soumya J.,NoC Application Mapping Optimization using Reinforcement Learning, ACM Transactions on Design Automation of Electronic Systems, 2022, Accepted. - https://dl.acm.org/doi/10.1145/3510381
5. P. Veda Bhanu, Rahul Govindan,  Rajat Kumar, Vishal Singh, Soumya J., Lingareddi C, Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA. IEEE Access, 9, 76759-76779, (2021) - https://ieeexplore.ieee.org/document/9438664
6. P. Veda Bhanu, Rahul Govindan, Plava Kattamuri, Soumya J., Lingareddi C, Flexible Spare Core Placement in Torus Topology based NoCs and its Validation on an FPGA, IEEE Access, 9, 45935-45954, (2021) - https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9380138
7. P. Veda Bhanu, Soumya J., Fault-Tolerant Application Mapping onto Mesh-of-Tree Topology based Network-on-Chip Design, Journal of Systems Architecture, 116, 102026, (2021) - https://www.sciencedirect.com/science/article/pii/S138376212100031X#:~:text=An%20Integer%20Linear%20Programming%20(ILP,%2DTree%20(MoT)%20network.
8. P. Veda Bhanu, Pranav Venkatesh Kulkarni, Soumya J., Butterfly-Fat-Tree topology based fault-tolerant Network-on-Chip design using particle swarm optimization, Journal of Experimental & Theoretical Artificial Intelligence, 31, 5, 781-799, (2019) - https://link.springer.com/chapter/10.1007/978-981-13-0761-4_108
9. P. Veda Bhanu, Pranav Venkatesh Kulkarni, Soumya J., Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement, ACM Journal on Emerging Technologies in Computing, 15, 1, 1-23, (2019) - https://dl.acm.org/doi/abs/10.1145/3269983#:~:text=Therefore%2C%20efficient%20fault%2Dtolerant%20methods,several%20benchmark%20applications%20into%20consideration.
10. Soumya J,  Niranjan Babu K, Santanu Chattopadhyay, Multi-Application Mapping onto a Switch based Reconfigurable Network-on-Chip Architecture, Journal of Circuits, Systems and Computers (JCSC), 26, 11 (2017) - https://www.worldscientific.com/doi/10.1142/S0218126617501742
11. Sandeep Dsouza, Soumya J, Santanu Chattopadhyay, Integrated Mapping and Synthesis Techniques for Network-on-Chip Topologies with Express Channels, ACM Transactions on Architecture and Code Optimization,(TACO) 12, 4, Article 40 (2016) - https://dl.acm.org/doi/10.1145/2831233
12. Soumya J., K. Naveen Kumar, Santanu Chattopadhyay, Integrated CoreSelection and Mapping for Mesh based Network-on-Chip Design with Irregular Core Sizes, Journal of Systems Architecture, 61, 9, 410-422 (2015) - https://www.sciencedirect.com/science/article/pii/S1383762115000843
13. Soumya J., Srijan Tiwary, Santanu Chattopadhyay, Area-Performance Trade-off in Floorplan Generation of Application-Specific Network-on-Chip with Soft Cores, Journal of Systems Architecture 61, 1, 1-11 (2015) - https://www.sciencedirect.com/science/article/pii/S1383762114001428
14. Soumya J., Ashish Sharma, Santanu Chattopadhyay, Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7, 2, Article 7 (2014) - https://dl.acm.org/doi/pdf/10.1145/2556944
15. Soumya J, Santanu Chattopadhyay, Application Specific Network-on-Chip Synthesis with flexible router placement,Journal of Systems Architecture 59, 361-371 (2013) - https://www.sciencedirect.com/science/article/pii/S1383762113000945
16. Santanu Kundu,Soumya J., Santanu Chattopadhyay, Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router, Microprocessors and Microsystems - Embedded Hardware Design 36(6),471-488 (2012) - https://www.sciencedirect.com/science/article/pii/S0141933112000877  

International Conferences:

1. Mekala Bindu Bhargavi, Sourish Ambati, Sri Parameswaran and Soumya J., 2025, Optimizing DNN Mapping on NoC-Based FPGA Accelerators Using Proximal Policy Optimization, ICEdge 2025 (Accepted)
2. Bhargavi, M.B., Rachakonda Komal Nayan, Sri Parameswaran, Soumya J., 2025, Cycle-Accurate ML-Based Power Modeling for RISC-V Cores Using RTL Simulations, SOCC 2025 (Accepted)
3. Bhargavi, M.B., Harshith, G.S.S. and Sri Parameswaran, Soumya J., 2024, July. Optimizing LU Decomposition with RISC-V Based Hardware Acceleration. In 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (pp. 210-215). IEEE.
4. Bhargavi, M.B., Subramanian, S.K. and Sri Parameswaran, Soumya J, 2024, December. Optimizing Convolutional Image Processing on RISC-V Using Branch Prediction on FPGA. In TENCON 20242024 IEEE Region 10 Conference (TENCON) (pp. 378-381). IEEE.
5. Bhargavi, M.B., Rokkam, S.S. and Sri Parameswaran, Soumya J, 2024, September. Automated Design and Configuration of RISC-V based NoC-MPSoC Framework on FPGA. In 2024 28th International Symposium on VLSI Design and Test (VDAT) (pp. 1-6). IEEE.
6. Choudhary, J., Varshith, P.S., Soumya, J. (2024). DAN: Deep Neural Network-Based Application Mapping for Optimized Network-on-Chip Design. In: Naik, N., Jenkins, P., Prajapat, S., Grace, P. (eds) Contributions Presented at The International Conference on Computing, Communication, Cybersecurity and AI, July 3–4, 2024, London, UK. C3AI 2024. Lecture Notes in Networks and Systems, vol 884. Springer, Cham. https://doi.org/10.1007/978-3-031-74443-3_7
7. N.Vamshi Krishna, Aruna and Soumya J., " Improving the Functional Coverage Closure of Network-on-Chip using Particle Swarm Optimization", International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2023
8. N Vamshi Krishna, Rahul Tripathy, Joshitha Marripudi and Soumya J., "Improving Functional Coverage of Network-On-Chip Using Differential Evolution", 18th International Conference on PhD Research in Microelectronics and Electronics (PRIME), 2023)
9. N.Vamshi Krishna, Jay P. Shah, Soumya J., "Improving the Functional Coverage Closure of Network-on-Chip Using Genetic Algorithm", 56th IEEE International Symposium on Circuits and Systems (ISCAS), 2023
10. Krishna, N.V., Chaudhary, A. and Soumya, J., 2024, January. FGG: Feedback Guided Generation to Accelerate Functional Coverage Closure on Network-on-Chip Processors. In 2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID) (pp. 702-707). IEEE.
11. Jitesh Choudhary, Vishesh Bindal, Soumya J, "MANA: Multi-Application Mapping onto Mesh Network-on-Chip using ANN", 26th International Symposium on VLSI Design and Test (VDAT), 2022, Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_24
12. Aparna Nair M K, Vishwas Vasuki Gautam, Abhishek Revinipati, Soumya J, "Implementation and Analysis of Convolution Image Filtering with RISC-V Based Architecture", 26th International Symposium on VLSI Design and Test (VDAT), 2022, Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_42
13. Aparna Nair M K, Police Manoj Kumar Reddy, Abijith Y.L., Venkatesh Rajagopalan, and Soumya J" Hardware Implementation of Network Interface Architecture for RISC-V based NoC-MPSoC Framework", 2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID), 2022, pp. 86-91, doi: 10.1109/VLSID2022.2022.00028.
14. M. K. Aparna Nair, P. Veda Bhanu, J. Soumyaand L. Reddy Cenkeramaddi " Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications," 2021 24th Euromicro Conference on Digital System Design (DSD), 2021, pp. 139-142, doi: 10.1109/DSD53832.2021.00030.
15. Jitesh Choudhary, Soumya J., and Linga Reddy Cenkarmaddi " RAMAN: Reinforcement Learning Inspired Algorithm for Mapping Applications onto Mesh NoC", 23rd ACM/IEEE International Workshop on System-Level Interconnect Pathfinding(SLIP), Nov 2021 (Accepted)
16. Jagadheesh. Samala, H. Takawale, Y. Chokhani, P. V. Bhanu and Soumya J., "Fault-Tolerant Routing Algorithm for Mesh based NoC using Reinforcement Learning," 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020, pp. 1-6, doi: 10.1109/VDAT50263.2020.9190340.
17. P. Veda Bhanu, Chetan Kumar V, Soumya J. "FILA: Fault-model for Interconnection Links in Application-Specific Network-on-Chip Design", 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, SPAIN, May 17-20 (Accepted). 
18. P. Veda Bhanu, Soumya J. "Fault-Tolerant Application-Specific Network-on-Chip Design using Discrete Particle Swarm Optimization", 2019 IEEE International Conference on Industrial and Information Systems (ICIIS), Peradeniya, Sri Lanka, December 18-20, 2019 (Article in press) 
19. Joshua Pushparaj, P. Veda Bhanu, Soumya J, "A Link Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips", 2019 IEEE International Symposium on Smart Electronic Systems (iSES), Rourkela, India, December 16-18, 2019 (Article in press)
20. Divyansh Mahajan, Swarali Patil, Wagh Vipul, Mohit Dangayach, P. Veda Bhanu, and Soumya J, "Design Automation of Network-on-Chip Prototype on FPGA", 2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), Manipal, India, August 11-12, 2019 (Article in press) 
21. P. Veda Bhanu, S. Jagadheesh, V. Bhat, G. Agarwal and J. Soumya, "FPGA Implementation of Novel Routing Algorithm for Buttery-Fat-Tree Topology based NoC Design," 2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Lausanne, Switzerland, 2019, pp. 69-72. doi:10.1109/PRIME.2019.8787747.
22. Mohit Upadhyay, Monil Shah, P. Veda Bhanu, Soumya J., and Linga Reddy Cenkarmaddiy., "Multi-Application based Network-on-Chip Design for Mesh-of-Tree topology using Global Mapping and Reconfigurable Architecture" The 32nd International Conference on VLSI Design, New Delhi, January 2019 
23. Mohit Upadhyay, Monil Shah,P. Veda Bhanu, Soumya J.,  Linga Reddy Cenkarmaddi, and Henning Idsøe,
    "A Novel Fault-Tolerant Routing Technique for Mesh-of-Tree Based Network-on-Chip Design", IEEE Region 10 International Conference (TENCON),  Jeju Island, Korea, October 2018 
24. P. Veda Bhanu, Pranav Venkatesh Kulkarni, Soumya J., Linga Reddy Cenkarmaddi, and Henning Idsøe,
    "Fault-Tolerant Network-on-Chip Design for Mesh-of-Tree Topology Using Particle Swarm Optimization", IEEE Region 10 International Conference (TENCON), Jeju Island, Korea, October 2018
25. Monil Shah, Mohit Upadhyay, Veda Bhanu P, Soumya J, and Linga Reddy Cenkeramaddi, "A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree based Network-on-Chips", Accepted in 22nd International Symposium on VLSI Design and Test (VDAT), June 2018.
26. P. Veda Bhanu, Pranav Kulkarni, Soumya J, Linga Reddy Cenkarmaddi, and Henning Idsøe, "Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement", Accepted in 14th Conference on PhD Research in Microelectronics and Electronics (PRIME), July 2018. 
27. Mohit Upadhyay, Monil Shah, P. Veda Bhanu, Soumya J, Linga Reddy Cenkeramaddi, "Fault tolerant Routing Methodology for Mesh-of-Tree based Network-on-Chips using Local Reconfiguration" Accepted in International Workshop on High Performance and Dynamic Reconfigurable Systems and Networks (DRSN), July 2018.
28. Divvya Sinha, Ashmita Roy, Kunchakuri Varun Kumar, Pranav Kulkarni, Soumya J, “Dn-FTR: Fault-Tolerant Routing Algorithm for Mesh based Network-on-Chip” Accepted IEEE International Conference on Recent Advances in Information Technology (RAIT), March 2018.
29.   P. Veda Bhanu, Pranav Venkatesh Kulkarni, U. Anil Kumar and Soumya J, “Buttery-Fat-Tree Topology based Fault-Tolerant Network-on-Chip Design using Particle Swarm Optimization” Accepted in International Conference on Harmony search, Soft Computing and Applications(ICHSA), February 2018.
30. Parth Shah, Kanniganti Abhishek, Soumya J, Fault-Tolerant Application Specific Network-on-Chip Design, 017 7th International Symposium on Embedded Computing and System Design (ISED), Durgapur, 2017, pp. 1-5. doi: 10.1109/ISED.2017.8303920
31. Sai Anirudh, Soumya J,  Routing Algorithm for Application-Specific Network-on-Chip with Irregular Core Sizes, 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Bhopal, 2017, pp. 56-60. doi: 10.1109/iNIS.2017.21
32. Soumya J, P S Phani Teja, Flexible Spare Core Placement for Fault-Tolerant Network-on-Chip Design, Accepted in Work-In-Progress, VDAT (2017)
33. Soumya J, P S Phani Teja, Flexible Spare Core Placement for Fault-Tolerant Network-on-Chip Design, Accepted in Work-In-Progress, DAC (2017)
34. Soumya J, Santanu Chattopadhyay, Application-Specific and Reconfigurable Network-on-Chip Design, Nominated for Best PhD Thesis, VLSID (2017) 
35. Sandeep Dsouza, Soumya J, Santanu Chattopadhyay, A Constructive Heuristic for Application Mapping onto an Express Channel based Network-on-Chip, VDAT 1-6 (2015)
36. Soumya J., Ashish Sharma, Santanu Chattopadhyay, A Locally Reconfigurable Network-on-Chip Architecture and Application Mappingonto it, VDAT 1-6 (2014)
37. Soumya J., Putta Venkatesh, Santanu Chattopadhyay, Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis, ISVLSI 2011 341-342 (2011)