About FPGA Hackathon
With the rapid growth of intelligent systems at the network edge, there is an increasing need for low-latency, low-power, and real-time AI inference directly on embedded hardware. Cloud-based AI solutions suffer from bandwidth limitations, high latency, privacy concerns, and increased energy consumption.
FPGA Hackathon 2026 focuses on Edge AI implemented on AMD/Xilinx FPGA platforms, encouraging participants to explore hardware-accelerated Edge AI inference engines by developing innovative, efficient, and application-driven solutions, implemented at the Verilog RTL level. The event emphasizes research-driven innovation and the development of industry-relevant skills, providing a competitive platform for undergraduate, postgraduate, and doctoral students across India.
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Problem Statement
Participants are required to design and implement hardware-accelerated Edge AI solutions on AMD/Xilinx FPGA platforms using Verilog RTL, targeting real-world applications such as Agriculture, Biomedical Systems, Traffic Management systems, Smart Energy Systems, and Defense systems. The solutions should emphasize real-time performance, energy efficiency, reliability, and on-device intelligence.
Hackathon at a Glance:
- Eligibility: BE, ME, MSc, and PhD students (open to students from all institutions across India)
- Team Size: 2 members per team
- Prize Pool: Up to ₹1.5 Lakhs
- Entry fee: Nil
- The hackathon will be conducted in two rounds.
- Round 1 (online): focused on hardware-accelerated Edge AI solutions using Verilog RTL
- Round 2 (offline): 6–8 teams shortlisted for the On-site Hackathon, and 10–15 teams shortlisted for the Poster Presentation during the final event.
- All participants qualifying for Round 2 will receive certificates
- Opportunity for Networking with Industry Experts and national-level visibility
Speakers
To be updated...
Round 1: Online Screening
- Develop an AI/ML model for a chosen real-world Edge AI application using suitable software tools (Python, MATLAB, C/C++, etc.) for training and validation. Use standard and publicly available datasets.
- Implement the inference stage of the model in RTL (Verilog) as a hardware accelerator.
- Demonstrate AI model operates at the edge emphasizing on real-time performance, low power consumption, and efficient hardware utilization
- FPGA prototyping using AMD/Xilinx FPGA platforms is strongly encouraged and will be given preference; however, correct RTL designs with validated simulation results will also be considered.
- Shortlisted teams will advance to Round 2 on-site Hackathon or Poster presentation
Round 2: Offline Final Competition (2 Days)
- Venue: BITS Pilani, Hyderabad Campus
Day 1 – On-site Hackathon
- Finalist teams will participate in the grand innovation challenge and deploy the inference stage of edge AI model for the chosen application at RTL level using real-time data and/or sensor interfacing on AMD/Xilinx FPGA platform with emphasis on real-time performance, low power consumption, and efficient hardware utilization.
- AMD/Xilinx FPGA boards, including ZedBoard, Zybo, and PYNQ, will be available for Round 2. Sensor and wireless interface modules (PMODs) will also be provided during the offline event.
- Teams may be required to implement an extended or modified problem statement during the hackathon.
- Industry/academia expert talks and hands-on workshop on hardware-accelerated Edge AI
Day 2 – Presentations & Outreach
- Technical presentations by hackathon finalist teams, poster session by shortlisted poster teams, industry/academia expert talks, panel discussion, Live-Demo/ hands-on workshop, final evaluation and announcement of results.
Application Domains:
- Agriculture: Modern agriculture increasingly relies on real-time data to improve yield, reduce waste, and optimize resource usage. Edge AI enables intelligent decision-making directly at farms, even in remote areas with limited connectivity. Proposed solutions may include, but are not limited to, crop disease detection from leaf images or sensor data, soil moisture classification for automated irrigation, and crop yield prediction using environmental parameters.
- Biomedical Systems: Healthcare systems rely on wearable and portable medical devices that require local, real-time data processing to ensure patient privacy and rapid response. Proposed solutions may include, but are not limited to, ECG/EEG signal classification for abnormality detection, heart rate anomaly detection, and medical image feature classification.
- Traffic Management System: Urban traffic congestion leads to increased fuel consumption, pollution, and delays. Edge AI enables localized, real-time traffic decision-making without reliance on centralized servers. Proposed solutions may include, but are not limited to, vehicle density estimation at intersections, adaptive traffic light control, and accident or congestion detection.
- Smart Energy System: Energy efficiency is a critical concern in smart buildings, factories, and smart grids. Edge AI enables intelligent, on-device energy management by optimizing resource usage without constant reliance on cloud connectivity. Proposed solutions may include, but are not limited to, load prediction and peak demand detection, as well as occupancy-based lighting or HVAC control.
- Defense System: Defense applications demand real-time, low-latency, and secure data processing in resource-constrained, mission-critical environments. Edge AI enables on-device intelligence that ensures fast response, reliability, and data security without reliance on cloud connectivity. Proposed solutions may include, but are not limited to, target detection or classification using sensor or image data, anomaly detection in radar, sonar, or surveillance signals, and multi-sensor data fusion for autonomous threat detection.
Registration Link
- Click here to Register. (https://forms.gle/X43LWxbF3oZSpFm78)
- Click here Round-1 Submission Link. (https://forms.gle/utP39b3sj4c3B4eGA)
Final submission and Evaluation:
- Complete Verilog RTL source code (project files in ZIP format)
- Video demonstration of implemented work (5–10 minutes).
- Technical report covering application overview and AI model architecture, design methodology, RTL Architecture, novelty and advantages over existing solutions. Round 1 report format
- Relevance to real-world problems, technical complexity, novelty, quality of hardware implementation, performance/metric comparison, completeness, and clarity of presentation.
Important Dates:
- Round 1 Registration Start: 3 February 2026.
- Registration Deadline: 20 Feb 2026.
Extended date till 1 March 2026. - Round 1 Submission Deadline: 15 March 2026.
Extended date till 20 March 2026. - Round 1 Result Declaration: 20 March 2026.
- Round 2 (Offline Event): Any two days between 10–12 April 2026.
Committee
To be updated...
Sponsors
To be updated...
Venue
Birla Institute of Technology and Science, Pilani - Hyderabad campus is one of the premier technical and science institutes of higher learning in India. It was established by Birla Institute of Technology and Science, Pilani (Rajasthan) as one of its latest campuses in the year 2008 with the first batch graduating in the year 2012. BITS, Pilani is one of India’s top technical and science universities established under Sec. 3 of the UGC act.
The sprawling campus is built amidst lush greenery spreading over 200 acres of land at Jawahar Nagar, Shameerpet, Hyderabad. Surrounded by natural beauty, the campus is about 70 kilometers away from Rajiv Gandhi International Airport, Shamshabad and 27 kilometers from Secunderabad railway station. The campus is easily accessible by road with a bus stop just outside the campus. Public transport (route# 212) runs every one hour from Secunderabad to the campus. The campus is in close proximity to many schools, medical facilities, and recreational centers.
The campus is built with state-of-the-art infrastructure without affecting the scenic beauty of the area. Modern laboratories, well-furnished classrooms, lecture theatre complexes, student activity center, auditorium, playground and modern ICT infrastructure, all come together to make BITS Pilani, Hyderabad campus a well-equipped campus.
Around 750 bright minds are admitted every year into first degree, higher degree and doctoral programmes of the institute through a single entrance test conducted by BITS, Pilani. Being a campus of BITS, Pilani, Hyderabad campus follows the same curriculum, teaching methodologies and educational practices of its’ parent campus. BITS, Pilani, Hyderabad campus is fully residential, housing over 3200 students, around 170 faculty members and 160 technical and support staff. The teaching faculty brings with them extensive research, teaching and industry experience to offer comprehensive education to students. Currently around 65 research projects are ongoing in the campus, most of which are supported by prominent funding agencies from India and abroad.
Campus life is vibrant and stimulating. Student calendars are filled with a healthy mix of extracurricular activities through various clubs and departments. There is a culture of freedom coupled with a holistic environment for multidimensional growth of a student personality. Over the past few years, students have been placed at multinational companies, government organizations, and research institutes across the globe. The students of the campus are truly ready to become the innovators of tomorrow.
Sponsorship & Organization
Organizing Committee
- Sponsored by: AMD
- Co-sponsored by: Institution’s Innovation Council (IIC), BITS Pilani Hyderabad Campus
- Hosted by: BITS Pilani
- Organized by: Department of EEE and IEEE Student Branch, BITS Pilani Hyderabad Campus
- Faculty Coordinator: Prof. Amit Kumar Panda, Dept. of EEE, BITS Pilani Hyderabad Campus
- AMD Coordinator: Mr. Santosh Yachareni, Fellow, AECG Design Engineering, AMD
- Student Coordinator: Vaibhav, Chairperson, IEEE Student Branch, BITSPH
- Student Co-Coordinator: Harsha, Vice-Chairperson, IEEE Student Branch, BITSPH
Reach BITS Pilani, Hyderabad Campus & Nearby Accommodations
From the Rajiv Gandhi International Airport (Shamshabad)
From the Railway Station
From Secunderabad railway station to BITS-Pilani, Hyderabad Campus one has to travel 22 KM on Rajiv Rahadari/ Karim Nagar Highway, up to Dongala Mysamma junction after Alankruta Resorts in Thumkunta Village and take a right turn towards Ghatkesar. After travelling 1.5 KMs on this road, there is again a diversion to the right leading to the Campus. BITS? sign boards indicating the directions are available on the way.
There is a direct Bus No. 212 from Secunderabad Railway station (Gurudwara Point) to BITS-Pilani Hyderabad Campus Main Gate Besides there are City Buses having numbers 211S, 211A, 211C, 211D, 211E, 211J, 211K, 211T, 211U, 567, 568, 569 fly from Secunderabad Railway Station to various destinations to the Campus side. Further, there are many APSRTC buses from Secunderabad, Jubilee bus-stand to KarimNagar, Siddhipet,Ramagundam,Gajwel, Cheriyal etc. People can board any of these buses, get down either at Thumkunta or Dongala Mysamma junction which is 1KM away and take an auto to the campus.
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CONTACTS
Prof. Amit Kumar Panda,
Phone: +91 40 66303746
Email: fpgahackathon@hyderabad.bits-pilani.ac.in
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BITS Hyderabad Campus
FACULTY CONTACTS
Faculty Coordinator:
Prof. Amit Kumar Panda,
Dept. of EEE, BITS Pilani Hyderabad Campus
AMD Coordinator:
Mr. Santosh Yachareni,
Fellow, AECG Design Engineering, AMD
Student Coordinator:
Vaibhav, Chairperson, IEEE Student
Branch, BITSPH
Student Co-Coordinator:
Harsha, Vice-Chairperson, IEEE
Student Branch, BITSPH
