BITS Pilani

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Title of the Ph.D. Thesis 
"Design of Energy Efficient Schedulers for Multicore Hard Real Time Systems."
Supervisors: Dr. Biju K. Raveendran and Prof. Bharat M. Deshpande 
 Project sponsored by BITS and SRCD under RIG and Faculty Interim scheme     TITLE: Design of a dynamic recommender system to make the resource access control protocols in hard real-time system energy efficient. 

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    An Institution Deemed to be University estd. vide Sec.3 of the UGC Act,1956 under notification # F.12-23/63.U-2 of Jun 18,1964

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