BITS Pilani

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Publications

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Publications

  • Arun S Nair, Louella Mesquita Colaco, Geeta Patil, Biju Raveendran, Sasikumar Punnekkatt, "MEDIATOR-A Mixed Criticality Deadline Honored Arbiter for Multi-core Real-time Systems", 23rd IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications (DS-RT), pages 1 - 8, 2019. 
  • Shubhangi K Gawali, Biju Raveendran, "DPVFS: a dynamic procrastination cum DVFS scheduler for multi-core hard real-time systems", International Journal of Embedded Systems, 11 (4), pages 461-471, 2019.
  • Geeta Patil, Neethu Bal Mallya, Biju Raveendran, "MOESIF: a MC/MP cache coherence protocol with improved bandwidth utilisation", International Journal of Embedded Systems, 11 (4), pages 493-507, 2019.
  • Alen Sabu, Biju Raveendran, Rituparna Ghosh, "SMILEY: a mixed-criticality real-time task scheduler for multicore systems", 22nd IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications (DS-RT), pages 1- 5, 2018.
  • Mayuri Digalwar, Biju Raveendran, Sudeept Mohan, "LAMCS: A leakage aware DVFS based mixed task set scheduler for multi-core processors", Sustainable Computing: Informatics and Systems, 15, pages 63-81, 2017.
  • Kajal Varma, Geeta Patil, Biju Raveendran, "DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems", 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), pages 207 - 212, 2017.
  • Mayuri Digalwar, Praveen Gahukar, Biju Raveendran, Sudeept Mohan, "Energy efficient real-time scheduling algorithm for mixed task set on multi-core processors", International Journal of Embedded Systems, 9 (6), pages 523-534, 2017.
  • Biju Raveendran, Pravin Joshi, Sahil Mittal, "eduCloud: a VM communication aware, migration efficient cloud for scientific computing", International Journal of Communication Networks and Distributed Systems, 18(3-4), pages 329 - 352, 2017.
  • Parag Panda, Geeta Patil, Biju Raveendran, "A survey on replacement strategies in cache memory for embedded systems", IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), pages 12 - 17, 2016.
  • Shubhangi K Gawali, Biju Raveendran, "DPS: A dynamic procrastination scheduler for multi-core/multi-processor hard real time systems", International Conference on Control, Decision and Information Technologies (CoDIT), pages 286 - 291, 2016.
  • Neethu Bal Mallya, Geeta Patil, Biju Raveendran, "Simulation based Performance Study of Cache Coherence Protocols", IEEE International Symposium on Nanoelectronic and Information Systems, pages 125 - 130, 2015.
  • Mayuri Digalwar, Pravin Gahukar, Sudeept Mohan, Biju Raveendran, "Stream: a simulation tool for energy efficient real time scheduling and analysis", 6th International Workshop on Analysis Tools and Methodologies for Embedded and Real Time Systems (WATERS 2015) in conjunction with 27th Euromicro Conference on Real-Time Systems (ECRTS 2015), 2015.
  • Neethu Bal Mallya, Geeta Patil, Biju Raveendran, "Way halted prediction cache: an energy efficient cache architecture for embedded processors", 28th International Conference on VLSI Design, pages 65-70, 2015.
  • Prashasti Baid, S Prashanth, Biju Raveendran, "LLFRP: An Energy Efficient Variant of LLF with Reduced Pre-emptions for Real–Time Systems", GSTF Journal on Computing (JoC), 3 (4), 2014.
  • Mayuri Digalwar, Sudeept Mohan, Biju Raveendran, "Dynamicvoltage and frequency scaling scheduling algorithm for mixed task set", 8th IEEE International Conference on Industrial and Information Systems, pages 643 - 648, 2013.
  • Mayuri Digalwar, Sudeept Mohan, Biju Raveendran, "Energy aware real time scheduling algorithm for mixed task set", IEEE International Conference on Advanced Electronic Systems (ICAES), pages 325-327, 2013.
  • Biju Raveendran, Sundar Balasubramaniam, S Gurunarayanan, "Evaluation of priority based real time scheduling algorithms: choices and tradeoffs", ACM symposium on Applied computing, pages 302-307, 2008.
  • Biju Raveendran, TSB Sudarshan, Avinash Patil, Komal Randive, S Gurunarayanan, "Predictive placement scheme in set-associative cache for energy efficient embedded systems", International Conference on Signal Processing, Communications and Networking, pages 152 - 157, 2008.
  • Biju Raveendran, TSB Sudarshan, P Dilip Kumar, Priyanka Tangudu, S Gurunarayanan, "LLRU: Late LRU Replacement Strategy for Power Efficient Embedded Cache", 15th International Conference on Advanced Computing and Communications (ADCOM 2007), pages 339 - 344, 2007.
  • Biju Raveendran, Janardan Prasad Misra, Karan Bhatnagar, S. Gurunarayanan, "EFFS: Efficient Flash File System for Wireless Sensor Nodes", ESA, pages 159-168, 2007.
  • Biju Raveendran, TSB Sudarshan, Avinash Patil, Komal B Randive, S Gurunarayanan, "An Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded System", ESA, pages 188-196, 2007.
  • Biju Raveendran, K Durga Prasad, Sundar Balasubramaniam, S Gurunarayanan, "Variants of priority scheduling algorithms for reducing context-switches in real-time systems", International Conference on Distributed Computing and Networking, pages 466-478, 2006.
  • Biju Raveendran, TSB Sudarshan, S Gurunarayanan, "Selective Placement Data Cache for Low Energy Embedded System", International Conference on Advanced Computing and Communications, pages 473-476, 2006.
  • Biju Raveendran, Sundar Balasubramaniam, K Durga Prasad, S Gurunarayanan, "A context-switch reduction heuristic for power-aware off-line scheduling", Asia-Pacific Conference on Advances in Computer Systems Architecture, pages 437-444, 2006.

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