BITS Pilani

  • Page last updated on Thursday, May 21, 2015





1. Ashish Mishra, "Design Flow Cycle and Simulation of Load Mover” in “International Journal of VLSI and Embedded Systems”.May,2015

2.  "Optimized Implementation of AES on LEON3” in “Journal of VLSI Design Tools and Technology (JoVDTTS)” on the April.,           2015.
3.  " Mapping and Partitioning of Task Graphs Using Kernighan-Lin/Fiduccia-Mattheyses Algorithm” publicated in “International         Journal of Emerging Technologies in Computational and Applied Sciences (IJETCAS)” ,March,2015.
4.  " Implementing Quadratic Function with Resource constraints using Microblaze Soft-core in Xilinx EDK” published in “The IUP       Journal of Telecommunication”,March, 2015.

5. "Iterative Algorithms for Periodic Scheduling of Synchronous Data Flow Graphs” published in “The IUP Journal of Telecommunication” ,March,2015.


1.A. Mishra, S. Singh, Y.Kulkarni, P. Halliyar ,K.S.Raju "Lossless Data Compression  using LZ77 and Huffman Algorithm using LEON3"NCVDES,IETE-Pilani-centre,CEERI,Oct 12-14,2011.


2.Mohanty, M.; Deb, D.; Konidala, A.; Mishra, A.; Kota, S.R." Framework for design with LEON3 system and testing with SHA-1 algorithm" International Conference on Communication and Industrial Application (ICCIA),pp. 1 - 4,Dec. 26-28,2011.

3.Ashish Mishra,Kritika garg,A.R. Asati Kota, S.R." Hardware Software Co-design using profiling and clustering" International Conference on Communication , Information and Computing Technology (ICCICT),Oct-19-20,2012.

4. Ashish Mishra, Nidhi Jayapalan, Harsha Rastogi, Tushar Agrawal,." Impact of Segmentation Distribution on Area and Delay in FPGA Routing Architectures" 3 rdInternational Advance Computing Conference ,Feb-22-23,2013.(IEEE conf)

5. Ashish Mishra, Hardik Mahasukh Shah, Lucky Sharan, Kota Solomon Raju,"VHDL Implementation of FFT Algorithm Using Vedic Multiplier" Proceeding of  Mobile and Embedded Technology International Conference(MECON),Jan-17-18-2013.

6. Ashish Mishra,A.R. Asati Kota, S.R "Scheduling of Dataflow Graphs on Partial Reconfigurable Hardware in Xilinx PR Flow", International conference on advanced electronic systems,(ICAES), Sep. 21-23,2013
7. Ashish Mishra, Dhruv Vakharia, Anirban Jyoti Hati , Kota Solomon Raju, "Hardware Software Partitioning of Task Graph Using Genetic Algorithm ”, IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014), Jaipur, May 9-11, 2014. 

Quick Links

    An institution deemed to be a University estd. vide Sec.3 of the UGC Act,1956 under notification # F.12-23/63.U-2 of Jun 18,1964

    © 2015 Centre for Software Development,SDET Unit, BITS-Pilani, India.

    Designed and developed by fractal | ink design studios