BITS Pilani

  • Page last updated on Monday, June 15, 2015

Publications

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Publications

Published

Journals:


1. A. Dubey, A. Mishra, S. Bhutada, "Comparative Study of CH  S tone Benchmarks on Xilinx Vivado High Level Synthesis Tool", International Journal of Engineering Research & Technology (IJERT), Vol. 4, Issue 01, Jan., 2015.

 

2. A. Mishra, K. P Kedar, H. M Shah, K S Raju " Implementing Quadratic Function with Resource constraints using Microblaze Soft-core in Xilinx EDK” , in IUP Journal of Telecommunication, Feb.  2015.

 

3. A. Mishra, D. Dave, V. Mittal, K. S. Raju "Iterative Algorithms for Periodic Scheduling of Synchronous Data Flow Graphs” in The IUP Journal of Telecommunication” , Feb. , 2015.

 

4.  A. Mishra, S. Kumar, J. Vasavada, K. S. Raju, "Optimized Implementation of AES on Leon3” in  Journal of VLSI Design Tools and Technology (JoVDTT).  Vol. 5, Issue 1, pp. 30-33,  Feb., 2015.

 

5.  A. Mishra, R. Jimit, A. R. Asati, K.S. Raju, " Mapping and Partitioning of Task Graphs Using Kernighan-Lin/Fiduccia-Mattheyses Algorithm” , in International Journal of Emerging Technologies in Computational and Applied Sciences (IJETCAS), pp. 58-61, Feb., 2015, pp. 58-61, March.

 

6. A. Mishra1, A. Javed, K. Bhargava, K. Tanmane, H. M. Shah, "Design Flow Cycle and Simulation of Load Mover” in International Journal of VLSI and Embedded Systems , May, 2015.

 

Conference:

1. A. Mishra, S. Singh, Y. Kulkarni, P. Halliya, K.S.Raju, "Lossless Data Compression  using LZ77 and Huffman Algorithm using LEON3", in National Conference on VLSI Design & Embedded Systems (NCVDES),IETE-Pilani-centre, CEERI, Oct. 12-14, 2011.

 

2. M. Mohanty, D. K. Deb, A. Mishra, K.S.Raju," Framework for design with LEON3 system and testing with SHA-1 algorithm", in International Conference on Communication and Industrial Application (ICCIA), pp.1- 4, Dec. 26-28, 2011.

 

3. A. Mishra, K. Garg, A.R. Asati, K.S. Raju, " Hardware Software Co-design using profiling and clustering", in International Conference on Communication, Information and Computing Technology (ICCICT), Oct. 19-20, 2012.

 

4. A. Mishra, N. Jayapalan, H. Rastogi, T. Agrawal," Impact of Segmentation Distribution on Area and Delay in FPGA Routing Architectures", in 3rd International Advance Computing Conference (IACC) ,Feb. 22-23,2013.

 

5. A. Mishra, H. M. Shah, L. Sharan, K. S. Raju, "VHDL Implementation of FFT Algorithm Using Vedic Multiplier", in Proceeding of  Mobile and Embedded Technology International Conference (MECON), Jan. 17-18-2013.

6. A. Mishra, A.R. Asati, K.S Raju ,"Scheduling of Dataflow Graphs on Partial Reconfigurable Hardware in Xilinx PR Flow", in International conference on advanced electronic systems,(ICAES), Sep. 21-23, 2013.

 

7. A. Mishra, D. Vakharia, A. J. Hati , K. S. Raju, "Hardware Software Partitioning of Task Graph Using Genetic Algorithm ”, in IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE), May 9-11, 2014. 

 

 

 

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